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Spdk/lib/nvme/nvme_quirks.c

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Replace most BSD 3-clause license text with SPDX identifier. Many open source projects have moved to using SPDX identifiers to specify license information, reducing the amount of boilerplate code in every source file. This patch replaces the bulk of SPDK .c, .cpp and Makefiles with the BSD-3-Clause identifier. Almost all of these files share the exact same license text, and this patch only modifies the files that contain the most common license text. There can be slight variations because the third clause contains company names - most say "Intel Corporation", but there are instances for Nvidia, Samsung, Eideticom and even "the copyright holder". Used a bash script to automate replacement of the license text with SPDX identifier which is checked into scripts/spdx.sh. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iaa88ab5e92ea471691dc298cfe41ebfb5d169780 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12904 Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Dong Yi <dongx.yi@intel.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Reviewed-by: Paul Luse <paul.e.luse@intel.com> Reviewed-by: <qun.wan@intel.com>
2022-06-03 19:15:11 +00:00
/* SPDX-License-Identifier: BSD-3-Clause
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
* Copyright (c) Intel Corporation.
* All rights reserved.
*/
#include "nvme_internal.h"
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
struct nvme_quirk {
env: add struct spdk_pci_id and getter function Use the new public PCI ID structure in the NVMe library to replace the previously private struct pci_id. Change-Id: I267d343917f60bdae949a824bc0fe67457cbbc0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-28 18:11:45 +00:00
struct spdk_pci_id id;
uint64_t flags;
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
};
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
static const struct nvme_quirk nvme_quirks[] = {
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: Fix up long lines in nvme_quirks.c This isn't the indentation pattern I would have chosen, but it's a complicated negotiation between what I want and what astyle will let me get away with. Change-Id: I4909587823931842ac3f227134e1d05e7d80da74 Signed-off-by: Ben Walker <benjamin.walker@intel.com>
2017-03-31 21:34:44 +00:00
NVME_INTEL_QUIRK_READ_LATENCY |
NVME_INTEL_QUIRK_WRITE_LATENCY |
lib/nvme: add a quirk for read zero after unmap Unmapped blocks on some older nvme devices will read zero even if the device does not explicitly define the unmap behavior. Change-Id: Ia825a406cbd01f89192c300cfe35013fb4aed715 Signed-off-by: Seth Howell <seth.howell@intel.com> Reviewed-on: https://review.gerrithub.io/372006 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
2017-07-31 19:56:30 +00:00
NVME_INTEL_QUIRK_STRIPING |
nvme: add NVME_QUIRK_DELAY_BEFORE_INIT quirk Currently we *always* wait 2 seconds before starting controller initialization during attach. This works around an issue where some older Intel NVMe SSDs could not handle MMIO writes too soon after a PCIe FLR (which would be triggered when VFIO was enabled). After further discussion with Intel experts, we know the SSD models that exhibit this issue. So we can quirk this so that only the older SSDs incur the extra delay. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Ieb408c24f6afd5bd5147d1c87239aa20f2d13511 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/466064 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com>
2019-08-22 10:09:53 +00:00
NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
nvme: add quirk for a minimum io queue size Some version of firmware on Intel SSDs exhibit poor performance with an IO queue size of 256 (the SPDK default). Add a quirk to account for this - and use the same size as the Linux driver (1024) instead. If the user specified a controller option to explicitly set the io_queue_size different than the default, the quirk will not take effect. Note that users can still override the io_queue_size when creating the qpair - this only changes the ctrlr's default io_queue_size. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iff0f7ab9856fc18f226f7171e5109bb8fe430969 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/432227 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Community-CI: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com> Community-CI: SPDK CI Jenkins <sys_sgci@intel.com>
2018-11-06 14:47:40 +00:00
NVME_QUIRK_DELAY_BEFORE_INIT |
NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
nvme: Fix up long lines in nvme_quirks.c This isn't the indentation pattern I would have chosen, but it's a complicated negotiation between what I want and what astyle will let me get away with. Change-Id: I4909587823931842ac3f227134e1d05e7d80da74 Signed-off-by: Ben Walker <benjamin.walker@intel.com>
2017-03-31 21:34:44 +00:00
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: update the nvme devices quirks. Change-Id: Ie5ea2e3929a3f0ce93e9dc9760c686370777635d Signed-off-by: Cunyin Chang <cunyin.chang@intel.com> Reviewed-on: https://review.gerrithub.io/376465 Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
2017-08-31 01:13:24 +00:00
NVME_INTEL_QUIRK_READ_LATENCY |
NVME_INTEL_QUIRK_WRITE_LATENCY |
nvme: Add nvme_quirk for intel P4800. Change-Id: Id2d38779b2178ce56391ac75781c1e41e4a83e1d Signed-off-by: Cunyin Chang <cunyin.chang@intel.com> Reviewed-on: https://review.gerrithub.io/375130 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2017-08-22 10:53:52 +00:00
NVME_INTEL_QUIRK_STRIPING |
nvme: add NVME_QUIRK_DELAY_BEFORE_INIT quirk Currently we *always* wait 2 seconds before starting controller initialization during attach. This works around an issue where some older Intel NVMe SSDs could not handle MMIO writes too soon after a PCIe FLR (which would be triggered when VFIO was enabled). After further discussion with Intel experts, we know the SSD models that exhibit this issue. So we can quirk this so that only the older SSDs incur the extra delay. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Ieb408c24f6afd5bd5147d1c87239aa20f2d13511 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/466064 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com>
2019-08-22 10:09:53 +00:00
NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
nvme: add quirk for a minimum io queue size Some version of firmware on Intel SSDs exhibit poor performance with an IO queue size of 256 (the SPDK default). Add a quirk to account for this - and use the same size as the Linux driver (1024) instead. If the user specified a controller option to explicitly set the io_queue_size different than the default, the quirk will not take effect. Note that users can still override the io_queue_size when creating the qpair - this only changes the ctrlr's default io_queue_size. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iff0f7ab9856fc18f226f7171e5109bb8fe430969 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/432227 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Community-CI: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com> Community-CI: SPDK CI Jenkins <sys_sgci@intel.com>
2018-11-06 14:47:40 +00:00
NVME_QUIRK_DELAY_BEFORE_INIT |
NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
nvme: Fix up long lines in nvme_quirks.c This isn't the indentation pattern I would have chosen, but it's a complicated negotiation between what I want and what astyle will let me get away with. Change-Id: I4909587823931842ac3f227134e1d05e7d80da74 Signed-off-by: Ben Walker <benjamin.walker@intel.com>
2017-03-31 21:34:44 +00:00
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A54, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: Add nvme_quirk for intel P4800. Change-Id: Id2d38779b2178ce56391ac75781c1e41e4a83e1d Signed-off-by: Cunyin Chang <cunyin.chang@intel.com> Reviewed-on: https://review.gerrithub.io/375130 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2017-08-22 10:53:52 +00:00
NVME_INTEL_QUIRK_READ_LATENCY |
NVME_INTEL_QUIRK_WRITE_LATENCY |
nvme: update the nvme devices quirks. Change-Id: Ie5ea2e3929a3f0ce93e9dc9760c686370777635d Signed-off-by: Cunyin Chang <cunyin.chang@intel.com> Reviewed-on: https://review.gerrithub.io/376465 Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
2017-08-31 01:13:24 +00:00
NVME_INTEL_QUIRK_STRIPING |
nvme: add quirk for a minimum io queue size Some version of firmware on Intel SSDs exhibit poor performance with an IO queue size of 256 (the SPDK default). Add a quirk to account for this - and use the same size as the Linux driver (1024) instead. If the user specified a controller option to explicitly set the io_queue_size different than the default, the quirk will not take effect. Note that users can still override the io_queue_size when creating the qpair - this only changes the ctrlr's default io_queue_size. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iff0f7ab9856fc18f226f7171e5109bb8fe430969 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/432227 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Community-CI: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com> Community-CI: SPDK CI Jenkins <sys_sgci@intel.com>
2018-11-06 14:47:40 +00:00
NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
nvme: add DELAY_BEFORE_INIT quirk to Intel 0x0A54 SSD This quirk was already applied to the 0x0A53 SSD, but is likely needed on 0x0A54 as well. Possible fix for issue #2231. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I36a48ab92d1698a411472f714b5108413bbc3c56 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/10162 Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Dong Yi <dongx.yi@intel.com> Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Community-CI: Mellanox Build Bot Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2021-11-09 14:03:41 +00:00
NVME_QUIRK_DELAY_BEFORE_INIT |
nvme: add quirk for a minimum io queue size Some version of firmware on Intel SSDs exhibit poor performance with an IO queue size of 256 (the SPDK default). Add a quirk to account for this - and use the same size as the Linux driver (1024) instead. If the user specified a controller option to explicitly set the io_queue_size different than the default, the quirk will not take effect. Note that users can still override the io_queue_size when creating the qpair - this only changes the ctrlr's default io_queue_size. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iff0f7ab9856fc18f226f7171e5109bb8fe430969 Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/432227 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Community-CI: Broadcom SPDK FC-NVMe CI <spdk-ci.pdl@broadcom.com> Community-CI: SPDK CI Jenkins <sys_sgci@intel.com>
2018-11-06 14:47:40 +00:00
NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
nvme: add quirks for Intel NVMe P4600 SSD Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iedfa8d3de8520836e184f7ef0925822fb705fc67 Reviewed-on: https://review.gerrithub.io/391672 Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Ziye Yang <optimistyzy@gmail.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
2017-12-13 20:47:21 +00:00
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A55, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add quirks for new NVMe controller Change-Id: Ice9da4b539b6c5955e449ec4d1ea18d580595caf Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/5857 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: <dongx.yi@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Ziye Yang <ziye.yang@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2021-01-11 04:44:02 +00:00
NVME_INTEL_QUIRK_READ_LATENCY |
NVME_INTEL_QUIRK_WRITE_LATENCY |
NVME_INTEL_QUIRK_STRIPING |
NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
},
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0B60, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add quirks for Intel NVMe P4600 SSD Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iedfa8d3de8520836e184f7ef0925822fb705fc67 Reviewed-on: https://review.gerrithub.io/391672 Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Ziye Yang <optimistyzy@gmail.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
2017-12-13 20:47:21 +00:00
NVME_INTEL_QUIRK_READ_LATENCY |
NVME_INTEL_QUIRK_WRITE_LATENCY |
NVME_INTEL_QUIRK_STRIPING |
nvme: add NO_SGL_FOR_DSM quirk for Intel P55XX SSDs Intel P55XX SSDs can support SGL feature but can't use Dataset Management command with SGL format, so add a quirk here for now, if the limitation was fixed in future, we can remvoe this. Also SPDK doesn't privoide scatter buffer API for DSM, so using PRP with DSM is totally fine. Change-Id: Ibe92f4deb5b8bc2077115f5b7244bc17be4f3b23 Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/5858 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com>
2021-01-11 05:16:23 +00:00
NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE |
NVME_QUIRK_NO_SGL_FOR_DSM
nvme: Fix up long lines in nvme_quirks.c This isn't the indentation pattern I would have chosen, but it's a complicated negotiation between what I want and what astyle will let me get away with. Change-Id: I4909587823931842ac3f227134e1d05e7d80da74 Signed-off-by: Ben Walker <benjamin.walker@intel.com>
2017-03-31 21:34:44 +00:00
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: Fix up long lines in nvme_quirks.c This isn't the indentation pattern I would have chosen, but it's a complicated negotiation between what I want and what astyle will let me get away with. Change-Id: I4909587823931842ac3f227134e1d05e7d80da74 Signed-off-by: Ben Walker <benjamin.walker@intel.com>
2017-03-31 21:34:44 +00:00
NVME_QUIRK_DELAY_BEFORE_CHK_RDY
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_SAMSUNG, 0xa821, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add chk_rdy quirk for some Samsung drives Add some known Samsung controllers to those requiring the quirk, NVME_QUIRK_DELAY_BEFORE_CHK_RDY. Addresses an issue for those who may not have later firmware that corrects the problem. Correspondingly, extend the delay from 2 secs to 2.5 secs. Change-Id: Iee773905a2a49711775042c061f6c347e0da85e9 Signed-off-by: Lance Hartmann <lance.hartmann@oracle.com> Reviewed-on: https://review.gerrithub.io/419273 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
2018-07-13 18:20:21 +00:00
NVME_QUIRK_DELAY_BEFORE_CHK_RDY
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_SAMSUNG, 0xa822, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add chk_rdy quirk for some Samsung drives Add some known Samsung controllers to those requiring the quirk, NVME_QUIRK_DELAY_BEFORE_CHK_RDY. Addresses an issue for those who may not have later firmware that corrects the problem. Correspondingly, extend the delay from 2 secs to 2.5 secs. Change-Id: Iee773905a2a49711775042c061f6c347e0da85e9 Signed-off-by: Lance Hartmann <lance.hartmann@oracle.com> Reviewed-on: https://review.gerrithub.io/419273 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
2018-07-13 18:20:21 +00:00
NVME_QUIRK_DELAY_BEFORE_CHK_RDY
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_VIRTUALBOX, 0x4e56, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC The VirtualBox emulated NVMe device will intermittently hang on the first read/write command after an I/O qpair has been allocated. The frequency of the hang diminishes if a delay is added after allocating the I/O qpair - until it disappears completely with a 100us delay. So add a quirk to insert this delay. Note - the 100us delay was tested by running the hello_world example app 50000 times. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I237e31b1b8a1a1e28262851ae0a21cd7345f0f1a
2017-04-29 19:21:32 +00:00
NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x5845, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add a quirk for QEMU emulated NVMe SSD When starting the QEMU NVMe SSD with "cmb_size_mb=XX" parameter, the controller memory buffer feature is enabled in the Guest, the SPDK NVMe driver running in the Guest will allocate the submission queue in the controller memory buffer by default, it will use memset and SSE instruction when copying NVMe command to the submission queue entry or zero the whole submission queue, inside the memset implementation the AVX2 instuction will be used if the CPU can support such feature. However, due to the limitation in the QEMU, the maximum access width to the PCI BAR space is set to 8 Bytes, SPDK will report illegal instruction in Guest. Here we add a quirk for the QEMU emulated NVMe. Fix issue #1362. Change-Id: Ib5e2e4198d39ce7f8455175f7db283db0b01eebf Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/2196 Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2020-05-06 02:17:15 +00:00
NVME_INTEL_QUIRK_NO_LOG_PAGES |
NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH
nvme: add a quirk for identify 0x2 Change-Id: I9cfc237a8514a1d323313851e14576ba2ba69077 Signed-off-by: Young Tack Jin <youngtack.jin@circuitblvd.com> Reviewed-on: https://review.gerrithub.io/410529 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-05-09 01:41:46 +00:00
},
nvme: add quirks for new RedHat QEMU NVMe dev/vendor ID QEMU 6.0 by default uses a RedHat dev/vendor ID rather than the Intel one that has always been used to date. We need the NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH quirk so that we do not use wide instructions to copy SQEs to a virtualized CMB, since QEMU does not support that. The NVME_INTEL_QUIRK_NO_LOG_PAGES quirk is only needed for devices with SPDK_PCI_VID_INTEL, so we do not need to carry this one over to the new REDHAT entry. Fixes issue #1986. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I3d339b3525e7c6ceb792eb9d143e7a922c19344d Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/8226 Reviewed-by: Paul Luse <paul.e.luse@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2021-06-09 17:00:45 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_REDHAT, 0x0010, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_CNEXLABS, 0x1f1f, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
lnvm: add a quirk for identify LightNVM device Change-Id: I841d7b47bc85498abb608944587e7b7585138263 Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com> Reviewed-on: https://review.gerrithub.io/411588 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Ziye Yang <optimistyzy@gmail.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-05-14 13:03:06 +00:00
NVME_QUIRK_IDENTIFY_CNS |
nvme: rename quirk from LIGHTNVM to OCSSD This is consistent with the Open Channel naming we are using elsewhere. Change-Id: Ib088359bed29a958f8b50e41cf34143a23429f54 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/413840 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
2018-06-05 16:56:50 +00:00
NVME_QUIRK_OCSSD
nvme: add a quirk for identify 0x2 Change-Id: I9cfc237a8514a1d323313851e14576ba2ba69077 Signed-off-by: Young Tack Jin <youngtack.jin@circuitblvd.com> Reviewed-on: https://review.gerrithub.io/410529 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-05-09 01:41:46 +00:00
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_VMWARE, 0x07f0, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add SHST_COMPLETE quirk for VMWare emulated SSDs VMWare Workstation NVMe emulation does not seem to write the SHST_COMPLETE bit within 10 seconds, resulting in an ERRLOG during detach/shutdown. So add a quirk to cover these VMWare SSDs. But rather than squashing the ERRLOG completely for these SSDs, just add a message instead indicating this is somewhat expected on these VMWare emulated SSDs. Fixes issue #676. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I3dfcb631feda639926fd712f1f41abb66cbf2096 Reviewed-on: https://review.gerrithub.io/c/445942 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
2019-02-22 12:51:32 +00:00
NVME_QUIRK_SHST_COMPLETE
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x2700, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
nvme: add security send/receive quirk for Intel 900P SSDs These SSDs set the oacs.security bit but do not actually support OPAL. So do not set the controller flag indicating SECURITY_SEND_RECV support in this case. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I7fcfeafcc8d9439a1c53c60a1aea1801923a2ce5 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3156 Community-CI: Broadcom CI Community-CI: Mellanox Build Bot Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-01 19:33:23 +00:00
NVME_QUIRK_OACS_SECURITY
},
nvme/quirk: add MDTS excludes interleaved metadata quirk The specification for Maximum Data Transfer Size (MDTS) says this field should include the length of metadata, if metadata is interleaved with the logical block data. However, some drives can support MDTS without counting the interleaved metadata, so for this case SPDK will only use data length without interleaved metadata length. Change-Id: I29920a25885699e2689be043b87122367be0e416 Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6813 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com>
2021-03-22 01:52:40 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x4140, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_QUIRK_MDTS_EXCLUDE_MD
},
nvme/quirks: don't use SGL for Huawei SSDs We see reports that Huawei SSDs can't handle hardware SGL properly, it requires additional alignment, so add a quirk here to force Huawei SSDs use PRP instead. Fix #2489. Change-Id: I20a57e754bc6ff8666d681191994818f2192decc Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12405 Community-CI: Mellanox Build Bot Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: wanghailiang <hailiangx.e.wang@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com> Reviewed-by: GangCao <gang.cao@intel.com> Reviewed-by: Dong Yi <dongx.yi@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2022-04-28 05:20:45 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_HUAWEI, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_QUIRK_NOT_USE_SGL
},
nvme: add admin queue size quirk for Hyper-V Hyper-V NVMe SSD controllers require admin queue size to be even multiples of a page. Add quirk to adjust the admin queue size if user overrides the default value to something other than an even multiple. As part of this change, set the quirks earlier when constructing a pcie controller, so that the quirks value can be used in the generic nvme_ctrlr_construct() function. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I417cd3cdc7e3ba512ec412f4876b0e0b7432341c Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/14220 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com>
2022-08-25 17:53:20 +00:00
{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_MICROSOFT, 0xb111, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE
},
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
{ {0x000000, 0x0000, 0x0000, 0x0000, 0x0000}, 0}
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
};
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
/* Compare each field. SPDK_PCI_ANY_ID in s1 matches everything */
static bool
env: add struct spdk_pci_id and getter function Use the new public PCI ID structure in the NVMe library to replace the previously private struct pci_id. Change-Id: I267d343917f60bdae949a824bc0fe67457cbbc0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-28 18:11:45 +00:00
pci_id_match(const struct spdk_pci_id *s1, const struct spdk_pci_id *s2)
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
{
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
if ((s1->class_id == SPDK_PCI_CLASS_ANY_ID || s1->class_id == s2->class_id) &&
(s1->vendor_id == SPDK_PCI_ANY_ID || s1->vendor_id == s2->vendor_id) &&
env: add struct spdk_pci_id and getter function Use the new public PCI ID structure in the NVMe library to replace the previously private struct pci_id. Change-Id: I267d343917f60bdae949a824bc0fe67457cbbc0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-28 18:11:45 +00:00
(s1->device_id == SPDK_PCI_ANY_ID || s1->device_id == s2->device_id) &&
(s1->subvendor_id == SPDK_PCI_ANY_ID || s1->subvendor_id == s2->subvendor_id) &&
(s1->subdevice_id == SPDK_PCI_ANY_ID || s1->subdevice_id == s2->subdevice_id)) {
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
return true;
}
return false;
}
uint64_t
env: add struct spdk_pci_id and getter function Use the new public PCI ID structure in the NVMe library to replace the previously private struct pci_id. Change-Id: I267d343917f60bdae949a824bc0fe67457cbbc0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-28 18:11:45 +00:00
nvme_get_quirks(const struct spdk_pci_id *id)
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
{
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
const struct nvme_quirk *quirk = nvme_quirks;
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
log: simplify SPDK_LOG_REGISTER_COMPONENT This patch removes the string from register component. Removed are all instances in libs or hardcoded in apps. Starting with this patch literal passed to register, serves as name for the flag. All instances of SPDK_LOG_* were replaced with just * in lowercase. No actual name change for flags occur in this patch. Affected are SPDK_LOG_REGISTER_COMPONENT() and SPDK_*LOG() macros. Signed-off-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Change-Id: I002b232fde57ecf9c6777726b181fc0341f1bb17 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/4495 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Mellanox Build Bot Reviewed-by: Anil Veerabhadrappa <anil.veerabhadrappa@broadcom.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Broadcom CI
2020-09-04 11:27:29 +00:00
SPDK_DEBUGLOG(nvme, "Searching for %04x:%04x [%04x:%04x]...\n",
nvme: add debug logs for matched quirks This can be enabled with -t nvme in debug builds. Change-Id: I4392d0a7decd65cc567fdf6fd56cac6db0424cd8 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401052 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:03:57 +00:00
id->vendor_id, id->device_id,
id->subvendor_id, id->subdevice_id);
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
while (quirk->id.vendor_id) {
if (pci_id_match(&quirk->id, id)) {
log: simplify SPDK_LOG_REGISTER_COMPONENT This patch removes the string from register component. Removed are all instances in libs or hardcoded in apps. Starting with this patch literal passed to register, serves as name for the flag. All instances of SPDK_LOG_* were replaced with just * in lowercase. No actual name change for flags occur in this patch. Affected are SPDK_LOG_REGISTER_COMPONENT() and SPDK_*LOG() macros. Signed-off-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Change-Id: I002b232fde57ecf9c6777726b181fc0341f1bb17 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/4495 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Mellanox Build Bot Reviewed-by: Anil Veerabhadrappa <anil.veerabhadrappa@broadcom.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Broadcom CI
2020-09-04 11:27:29 +00:00
SPDK_DEBUGLOG(nvme, "Matched quirk %04x:%04x [%04x:%04x]:\n",
nvme: add debug logs for matched quirks This can be enabled with -t nvme in debug builds. Change-Id: I4392d0a7decd65cc567fdf6fd56cac6db0424cd8 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401052 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:03:57 +00:00
quirk->id.vendor_id, quirk->id.device_id,
quirk->id.subvendor_id, quirk->id.subdevice_id);
#define PRINT_QUIRK(quirk_flag) \
do { \
if (quirk->flags & (quirk_flag)) { \
log: simplify SPDK_LOG_REGISTER_COMPONENT This patch removes the string from register component. Removed are all instances in libs or hardcoded in apps. Starting with this patch literal passed to register, serves as name for the flag. All instances of SPDK_LOG_* were replaced with just * in lowercase. No actual name change for flags occur in this patch. Affected are SPDK_LOG_REGISTER_COMPONENT() and SPDK_*LOG() macros. Signed-off-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Change-Id: I002b232fde57ecf9c6777726b181fc0341f1bb17 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/4495 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Mellanox Build Bot Reviewed-by: Anil Veerabhadrappa <anil.veerabhadrappa@broadcom.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Broadcom CI
2020-09-04 11:27:29 +00:00
SPDK_DEBUGLOG(nvme, "Quirk enabled: %s\n", #quirk_flag); \
nvme: add debug logs for matched quirks This can be enabled with -t nvme in debug builds. Change-Id: I4392d0a7decd65cc567fdf6fd56cac6db0424cd8 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401052 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:03:57 +00:00
} \
} while (0)
PRINT_QUIRK(NVME_INTEL_QUIRK_READ_LATENCY);
PRINT_QUIRK(NVME_INTEL_QUIRK_WRITE_LATENCY);
PRINT_QUIRK(NVME_QUIRK_DELAY_BEFORE_CHK_RDY);
PRINT_QUIRK(NVME_INTEL_QUIRK_STRIPING);
PRINT_QUIRK(NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC);
PRINT_QUIRK(NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE);
nvme: add a quirk for identify 0x2 Change-Id: I9cfc237a8514a1d323313851e14576ba2ba69077 Signed-off-by: Young Tack Jin <youngtack.jin@circuitblvd.com> Reviewed-on: https://review.gerrithub.io/410529 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-05-09 01:41:46 +00:00
PRINT_QUIRK(NVME_QUIRK_IDENTIFY_CNS);
nvme: rename quirk from LIGHTNVM to OCSSD This is consistent with the Open Channel naming we are using elsewhere. Change-Id: Ib088359bed29a958f8b50e41cf34143a23429f54 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/413840 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
2018-06-05 16:56:50 +00:00
PRINT_QUIRK(NVME_QUIRK_OCSSD);
nvme: add debug logs for matched quirks This can be enabled with -t nvme in debug builds. Change-Id: I4392d0a7decd65cc567fdf6fd56cac6db0424cd8 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401052 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:03:57 +00:00
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
return quirk->flags;
}
quirk++;
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
}
nvme: add debug logs for matched quirks This can be enabled with -t nvme in debug builds. Change-Id: I4392d0a7decd65cc567fdf6fd56cac6db0424cd8 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401052 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:03:57 +00:00
log: simplify SPDK_LOG_REGISTER_COMPONENT This patch removes the string from register component. Removed are all instances in libs or hardcoded in apps. Starting with this patch literal passed to register, serves as name for the flag. All instances of SPDK_LOG_* were replaced with just * in lowercase. No actual name change for flags occur in this patch. Affected are SPDK_LOG_REGISTER_COMPONENT() and SPDK_*LOG() macros. Signed-off-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Change-Id: I002b232fde57ecf9c6777726b181fc0341f1bb17 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/4495 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Mellanox Build Bot Reviewed-by: Anil Veerabhadrappa <anil.veerabhadrappa@broadcom.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Broadcom CI
2020-09-04 11:27:29 +00:00
SPDK_DEBUGLOG(nvme, "No quirks found.\n");
nvme: add debug logs for matched quirks This can be enabled with -t nvme in debug builds. Change-Id: I4392d0a7decd65cc567fdf6fd56cac6db0424cd8 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401052 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:03:57 +00:00
nvme: fix return value of nvme_get_quirks() This function returns uint64_t, but the existing code was returning the bool 'false' (which is also 0, so there is no functional change). Change-Id: I546b15974c2d9e4107efe262950e3eb5613e0e9f Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-on: https://review.gerrithub.io/401051 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-02-22 20:04:31 +00:00
return 0;
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
}
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