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nvme: Add Intel NVMe device supported feature quirks

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This patch adds Intel NVMe device list and overrides the
supported log pages according to the quirk list.

In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are
supported on Intel DC P3x00 devices despite not being listed in the
Intel vendor-specific log page directory.

Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0
Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
This commit is contained in:
Cunyin Chang 2016-01-27 15:08:53 +08:00 committed by Daniel Verkamp
parent c02b179490
commit aa2970b9f3
8 changed files with 132 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/spdk/pci.h
View File

@ -40,6 +40,8 @@
#define spdk_pci_device_get_func(dev) (dev->func)
#define spdk_pci_device_get_vendor_id(dev) (dev->vendor_id)
#define spdk_pci_device_get_device_id(dev) (dev->device_id)
#define spdk_pci_device_get_subvendor_id(dev) (dev->subvendor_id)
#define spdk_pci_device_get_subdevice_id(dev) (dev->subdevice_id)
#define PCI_CFG_SIZE 256
#define PCI_EXT_CAP_ID_SN 0x03

11
include/spdk/pci_ids.h
View File

@ -34,6 +34,15 @@
#ifndef __PCI_IDS_H__
#define __PCI_IDS_H__
#define PCI_VENDOR_ID_INTEL 0x8086
#include <stdint.h>
#define PCI_VENDOR_ID_INTEL 0x8086
struct pci_id {
uint16_t vendor_id;
uint16_t dev_id;
uint16_t sub_vendor_id;
uint16_t sub_dev_id;
};
#endif /* __PCI_IDS_H__ */

2
lib/nvme/Makefile
View File

@ -36,7 +36,7 @@ include $(SPDK_ROOT_DIR)/mk/spdk.common.mk
CFLAGS += $(DPDK_INC) -include $(CONFIG_NVME_IMPL)
C_SRCS = nvme_ctrlr_cmd.c nvme_ctrlr.c nvme_ns_cmd.c nvme_ns.c nvme_qpair.c nvme.c
C_SRCS = nvme_ctrlr_cmd.c nvme_ctrlr.c nvme_ns_cmd.c nvme_ns.c nvme_qpair.c nvme.c nvme_intel.c
LIB = libspdk_nvme.a

20
lib/nvme/nvme_ctrlr.c
View File

@ -30,9 +30,10 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <pciaccess.h>
#include "nvme_internal.h"
#include "spdk/nvme_intel.h"
#include "spdk/pci.h"
/**
* \file
*
@ -45,15 +46,26 @@ static void
nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr,
struct nvme_intel_log_page_directory *log_page_directory)
{
struct pci_device *dev;
struct pci_id pci_id;
if (ctrlr->cdata.vid != PCI_VENDOR_ID_INTEL || log_page_directory == NULL)
return;
dev = ctrlr->devhandle;
pci_id.vendor_id = spdk_pci_device_get_vendor_id(dev);
pci_id.dev_id = spdk_pci_device_get_device_id(dev);
pci_id.sub_vendor_id = spdk_pci_device_get_subvendor_id(dev);
pci_id.sub_dev_id = spdk_pci_device_get_subdevice_id(dev);
ctrlr->log_page_supported[NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
if (log_page_directory->read_latency_log_len) {
if (log_page_directory->read_latency_log_len ||
nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_READ_LATENCY)) {
ctrlr->log_page_supported[NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
}
if (log_page_directory->write_latency_log_len) {
if (log_page_directory->write_latency_log_len ||
nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_WRITE_LATENCY)) {
ctrlr->log_page_supported[NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
}
if (log_page_directory->temperature_statistics_log_len) {

64
lib/nvme/nvme_intel.c Normal file
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@ -0,0 +1,64 @@
/*-
* BSD LICENSE
*
* Copyright (c) Intel Corporation.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "nvme_internal.h"
/** \file
* Intel specific data structures and functions.
*/
struct nvme_intel_quirk {
struct pci_id id;
uint64_t flags;
};
static const struct nvme_intel_quirk intel_p3x00[] = {
{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
{{0x0000, 0x0000, 0x0000, 0x0000}, 0 }
};
bool nvme_intel_has_quirk(struct pci_id *id, uint64_t quirk)
{
const struct nvme_intel_quirk *intel_quirk = intel_p3x00;
while (intel_quirk->id.vendor_id) {
if (!memcmp(&intel_quirk->id, id, sizeof(*id)) && (intel_quirk->flags & quirk))
return true;
intel_quirk++;
}
return false;
}

15
lib/nvme/nvme_internal.h
View File

@ -54,6 +54,19 @@
#include "spdk/mmio.h"
#include "spdk/pci_ids.h"
#include "spdk/nvme_intel.h"
#include "spdk/pci_ids.h"
/*
* Some Intel devices support vendor-unique read latency log page even
* though the log page directory says otherwise.
*/
#define NVME_INTEL_QUIRK_READ_LATENCY 0x1
/*
* Some Intel devices support vendor-unique write latency log page even
* though the log page directory says otherwise.
*/
#define NVME_INTEL_QUIRK_WRITE_LATENCY 0x2
#define NVME_MAX_PRP_LIST_ENTRIES (32)
@ -440,5 +453,5 @@ struct nvme_request *nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg
struct nvme_request *nvme_allocate_request_contig(void *buffer, uint32_t payload_size,
nvme_cb_fn_t cb_fn, void *cb_arg);
void nvme_free_request(struct nvme_request *req);
bool nvme_intel_has_quirk(struct pci_id *id, uint64_t quirk);
#endif /* __NVME_INTERNAL_H__ */

1
test/lib/nvme/unit/nvme_ctrlr_c/Makefile
View File

@ -34,6 +34,7 @@
SPDK_ROOT_DIR := $(CURDIR)/../../../../..
TEST_FILE = nvme_ctrlr_ut.c
OTHER_FILES = nvme_intel.c
include $(SPDK_ROOT_DIR)/mk/nvme.unittest.mk

28
test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c
View File

@ -146,7 +146,6 @@ nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
return 0;
}
struct nvme_request *
nvme_allocate_request(const struct nvme_payload *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn,
void *cb_arg)
@ -179,7 +178,6 @@ nvme_allocate_request_contig(void *buffer, uint32_t payload_size, nvme_cb_fn_t c
return nvme_allocate_request(&payload, payload_size, cb_fn, cb_arg);
}
struct nvme_request *
nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
{
@ -203,17 +201,20 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void)
bool res;
struct nvme_controller ctrlr = {};
struct nvme_intel_log_page_directory payload = {};
struct pci_device device = {};
/* set a invalid vendor id */
ctrlr.cdata.vid = 0xFFFF;
memset(&payload, 0, sizeof(struct nvme_intel_log_page_directory));
ctrlr.devhandle = &device;
nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE);
CU_ASSERT(res == false);
/* set valid vendor id and log page directory*/
ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL;
payload.temperature_statistics_log_len = 1;
memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY);
CU_ASSERT(res == true);
@ -223,6 +224,25 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void)
CU_ASSERT(res == false);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_SMART);
CU_ASSERT(res == false);
/* set valid vendor id, device id and sub device id*/
ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL;
payload.temperature_statistics_log_len = 0;
device.vendor_id = PCI_VENDOR_ID_INTEL;
device.device_id = 0x0953;
device.subvendor_id = PCI_VENDOR_ID_INTEL;
device.subdevice_id = 0x3702;
memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY);
CU_ASSERT(res == true);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE);
CU_ASSERT(res == false);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_READ_CMD_LATENCY);
CU_ASSERT(res == true);
res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_SMART);
CU_ASSERT(res == false);
}
static void