nvme: Add Intel NVMe device supported feature quirks
This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
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@ -40,6 +40,8 @@
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#define spdk_pci_device_get_func(dev) (dev->func)
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#define spdk_pci_device_get_vendor_id(dev) (dev->vendor_id)
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#define spdk_pci_device_get_device_id(dev) (dev->device_id)
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#define spdk_pci_device_get_subvendor_id(dev) (dev->subvendor_id)
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#define spdk_pci_device_get_subdevice_id(dev) (dev->subdevice_id)
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#define PCI_CFG_SIZE 256
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#define PCI_EXT_CAP_ID_SN 0x03
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@ -34,6 +34,15 @@
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#ifndef __PCI_IDS_H__
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#define __PCI_IDS_H__
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#define PCI_VENDOR_ID_INTEL 0x8086
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#include <stdint.h>
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#define PCI_VENDOR_ID_INTEL 0x8086
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struct pci_id {
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uint16_t vendor_id;
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uint16_t dev_id;
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uint16_t sub_vendor_id;
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uint16_t sub_dev_id;
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};
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#endif /* __PCI_IDS_H__ */
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@ -36,7 +36,7 @@ include $(SPDK_ROOT_DIR)/mk/spdk.common.mk
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CFLAGS += $(DPDK_INC) -include $(CONFIG_NVME_IMPL)
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C_SRCS = nvme_ctrlr_cmd.c nvme_ctrlr.c nvme_ns_cmd.c nvme_ns.c nvme_qpair.c nvme.c
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C_SRCS = nvme_ctrlr_cmd.c nvme_ctrlr.c nvme_ns_cmd.c nvme_ns.c nvme_qpair.c nvme.c nvme_intel.c
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LIB = libspdk_nvme.a
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@ -30,9 +30,10 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <pciaccess.h>
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#include "nvme_internal.h"
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#include "spdk/nvme_intel.h"
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#include "spdk/pci.h"
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/**
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* \file
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*
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@ -45,15 +46,26 @@ static void
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nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr,
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struct nvme_intel_log_page_directory *log_page_directory)
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{
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struct pci_device *dev;
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struct pci_id pci_id;
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if (ctrlr->cdata.vid != PCI_VENDOR_ID_INTEL || log_page_directory == NULL)
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return;
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dev = ctrlr->devhandle;
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pci_id.vendor_id = spdk_pci_device_get_vendor_id(dev);
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pci_id.dev_id = spdk_pci_device_get_device_id(dev);
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pci_id.sub_vendor_id = spdk_pci_device_get_subvendor_id(dev);
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pci_id.sub_dev_id = spdk_pci_device_get_subdevice_id(dev);
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ctrlr->log_page_supported[NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
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if (log_page_directory->read_latency_log_len) {
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if (log_page_directory->read_latency_log_len ||
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nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_READ_LATENCY)) {
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ctrlr->log_page_supported[NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
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}
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if (log_page_directory->write_latency_log_len) {
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if (log_page_directory->write_latency_log_len ||
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nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_WRITE_LATENCY)) {
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ctrlr->log_page_supported[NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
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}
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if (log_page_directory->temperature_statistics_log_len) {
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64
lib/nvme/nvme_intel.c
Normal file
64
lib/nvme/nvme_intel.c
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@ -0,0 +1,64 @@
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/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "nvme_internal.h"
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/** \file
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* Intel specific data structures and functions.
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*/
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struct nvme_intel_quirk {
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struct pci_id id;
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uint64_t flags;
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};
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static const struct nvme_intel_quirk intel_p3x00[] = {
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{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY },
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{{0x0000, 0x0000, 0x0000, 0x0000}, 0 }
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};
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bool nvme_intel_has_quirk(struct pci_id *id, uint64_t quirk)
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{
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const struct nvme_intel_quirk *intel_quirk = intel_p3x00;
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while (intel_quirk->id.vendor_id) {
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if (!memcmp(&intel_quirk->id, id, sizeof(*id)) && (intel_quirk->flags & quirk))
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return true;
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intel_quirk++;
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}
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return false;
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}
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@ -54,6 +54,19 @@
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#include "spdk/mmio.h"
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#include "spdk/pci_ids.h"
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#include "spdk/nvme_intel.h"
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#include "spdk/pci_ids.h"
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/*
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* Some Intel devices support vendor-unique read latency log page even
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* though the log page directory says otherwise.
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*/
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#define NVME_INTEL_QUIRK_READ_LATENCY 0x1
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/*
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* Some Intel devices support vendor-unique write latency log page even
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* though the log page directory says otherwise.
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*/
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#define NVME_INTEL_QUIRK_WRITE_LATENCY 0x2
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#define NVME_MAX_PRP_LIST_ENTRIES (32)
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@ -440,5 +453,5 @@ struct nvme_request *nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg
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struct nvme_request *nvme_allocate_request_contig(void *buffer, uint32_t payload_size,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_free_request(struct nvme_request *req);
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bool nvme_intel_has_quirk(struct pci_id *id, uint64_t quirk);
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#endif /* __NVME_INTERNAL_H__ */
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@ -34,6 +34,7 @@
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SPDK_ROOT_DIR := $(CURDIR)/../../../../..
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TEST_FILE = nvme_ctrlr_ut.c
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OTHER_FILES = nvme_intel.c
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include $(SPDK_ROOT_DIR)/mk/nvme.unittest.mk
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@ -146,7 +146,6 @@ nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
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return 0;
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}
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struct nvme_request *
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nvme_allocate_request(const struct nvme_payload *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn,
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void *cb_arg)
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@ -179,7 +178,6 @@ nvme_allocate_request_contig(void *buffer, uint32_t payload_size, nvme_cb_fn_t c
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return nvme_allocate_request(&payload, payload_size, cb_fn, cb_arg);
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}
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struct nvme_request *
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nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
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{
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@ -203,17 +201,20 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void)
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bool res;
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struct nvme_controller ctrlr = {};
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struct nvme_intel_log_page_directory payload = {};
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struct pci_device device = {};
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/* set a invalid vendor id */
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ctrlr.cdata.vid = 0xFFFF;
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memset(&payload, 0, sizeof(struct nvme_intel_log_page_directory));
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ctrlr.devhandle = &device;
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nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE);
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CU_ASSERT(res == false);
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/* set valid vendor id and log page directory*/
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ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL;
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payload.temperature_statistics_log_len = 1;
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memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
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nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY);
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CU_ASSERT(res == true);
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@ -223,6 +224,25 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void)
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CU_ASSERT(res == false);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_SMART);
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CU_ASSERT(res == false);
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/* set valid vendor id, device id and sub device id*/
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ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL;
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payload.temperature_statistics_log_len = 0;
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device.vendor_id = PCI_VENDOR_ID_INTEL;
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device.device_id = 0x0953;
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device.subvendor_id = PCI_VENDOR_ID_INTEL;
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device.subdevice_id = 0x3702;
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memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported));
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nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY);
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CU_ASSERT(res == true);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE);
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CU_ASSERT(res == false);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_READ_CMD_LATENCY);
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CU_ASSERT(res == true);
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res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_SMART);
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CU_ASSERT(res == false);
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}
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static void
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