b90d7b5b43
Hyper-V NVMe SSD controllers require admin queue size to be even multiples of a page. Add quirk to adjust the admin queue size if user overrides the default value to something other than an even multiple. As part of this change, set the quirks earlier when constructing a pcie controller, so that the quirks value can be used in the generic nvme_ctrlr_construct() function. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I417cd3cdc7e3ba512ec412f4876b0e0b7432341c Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/14220 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com>
147 lines
4.9 KiB
C
147 lines
4.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*/
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#include "nvme_internal.h"
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struct nvme_quirk {
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struct spdk_pci_id id;
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uint64_t flags;
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};
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static const struct nvme_quirk nvme_quirks[] = {
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A54, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_DELAY_BEFORE_INIT |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0A55, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x0B60, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_READ_LATENCY |
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NVME_INTEL_QUIRK_WRITE_LATENCY |
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NVME_INTEL_QUIRK_STRIPING |
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NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE |
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NVME_QUIRK_NO_SGL_FOR_DSM
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_SAMSUNG, 0xa821, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_SAMSUNG, 0xa822, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_VIRTUALBOX, 0x4e56, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x5845, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_INTEL_QUIRK_NO_LOG_PAGES |
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NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_REDHAT, 0x0010, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_CNEXLABS, 0x1f1f, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_IDENTIFY_CNS |
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NVME_QUIRK_OCSSD
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_VMWARE, 0x07f0, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_SHST_COMPLETE
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x2700, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_OACS_SECURITY
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_INTEL, 0x4140, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_MDTS_EXCLUDE_MD
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_HUAWEI, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_NOT_USE_SGL
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},
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{ {SPDK_PCI_CLASS_NVME, SPDK_PCI_VID_MICROSOFT, 0xb111, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE
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},
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{ {0x000000, 0x0000, 0x0000, 0x0000, 0x0000}, 0}
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};
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/* Compare each field. SPDK_PCI_ANY_ID in s1 matches everything */
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static bool
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pci_id_match(const struct spdk_pci_id *s1, const struct spdk_pci_id *s2)
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{
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if ((s1->class_id == SPDK_PCI_CLASS_ANY_ID || s1->class_id == s2->class_id) &&
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(s1->vendor_id == SPDK_PCI_ANY_ID || s1->vendor_id == s2->vendor_id) &&
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(s1->device_id == SPDK_PCI_ANY_ID || s1->device_id == s2->device_id) &&
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(s1->subvendor_id == SPDK_PCI_ANY_ID || s1->subvendor_id == s2->subvendor_id) &&
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(s1->subdevice_id == SPDK_PCI_ANY_ID || s1->subdevice_id == s2->subdevice_id)) {
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return true;
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}
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return false;
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}
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uint64_t
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nvme_get_quirks(const struct spdk_pci_id *id)
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{
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const struct nvme_quirk *quirk = nvme_quirks;
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SPDK_DEBUGLOG(nvme, "Searching for %04x:%04x [%04x:%04x]...\n",
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id->vendor_id, id->device_id,
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id->subvendor_id, id->subdevice_id);
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while (quirk->id.vendor_id) {
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if (pci_id_match(&quirk->id, id)) {
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SPDK_DEBUGLOG(nvme, "Matched quirk %04x:%04x [%04x:%04x]:\n",
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quirk->id.vendor_id, quirk->id.device_id,
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quirk->id.subvendor_id, quirk->id.subdevice_id);
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#define PRINT_QUIRK(quirk_flag) \
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do { \
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if (quirk->flags & (quirk_flag)) { \
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SPDK_DEBUGLOG(nvme, "Quirk enabled: %s\n", #quirk_flag); \
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} \
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} while (0)
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PRINT_QUIRK(NVME_INTEL_QUIRK_READ_LATENCY);
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PRINT_QUIRK(NVME_INTEL_QUIRK_WRITE_LATENCY);
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PRINT_QUIRK(NVME_QUIRK_DELAY_BEFORE_CHK_RDY);
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PRINT_QUIRK(NVME_INTEL_QUIRK_STRIPING);
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PRINT_QUIRK(NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC);
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PRINT_QUIRK(NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE);
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PRINT_QUIRK(NVME_QUIRK_IDENTIFY_CNS);
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PRINT_QUIRK(NVME_QUIRK_OCSSD);
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return quirk->flags;
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}
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quirk++;
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}
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SPDK_DEBUGLOG(nvme, "No quirks found.\n");
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return 0;
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}
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