2d686707df
Implement memory barrier for LOONGARCH platforms. Change-Id: I44f5e63e6eb3f8bf98e965a22fb86f94e727061d Signed-off-by: Xue Liu <liuxue@loongson.cn> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/16082 Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (c) 2017, IBM Corporation.
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* All rights reserved.
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*/
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/** \file
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* Memory barriers
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*/
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#ifndef SPDK_BARRIER_H
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#define SPDK_BARRIER_H
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#include "spdk/stdinc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Compiler memory barrier */
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#define spdk_compiler_barrier() __asm volatile("" ::: "memory")
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/** Read memory barrier */
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#define spdk_rmb() _spdk_rmb()
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/** Write memory barrier */
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#define spdk_wmb() _spdk_wmb()
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/** Full read/write memory barrier */
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#define spdk_mb() _spdk_mb()
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/** SMP read memory barrier. */
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#define spdk_smp_rmb() _spdk_smp_rmb()
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/** SMP write memory barrier. */
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#define spdk_smp_wmb() _spdk_smp_wmb()
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/** SMP read/write memory barrier. */
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#define spdk_smp_mb() _spdk_smp_mb()
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/** Invalidate data cache, input is data pointer */
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#define spdk_ivdt_dcache(pdata) _spdk_ivdt_dcache(pdata)
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#ifdef __PPC64__
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#define _spdk_rmb() __asm volatile("sync" ::: "memory")
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#define _spdk_wmb() __asm volatile("sync" ::: "memory")
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#define _spdk_mb() __asm volatile("sync" ::: "memory")
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#define _spdk_smp_rmb() __asm volatile("lwsync" ::: "memory")
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#define _spdk_smp_wmb() __asm volatile("lwsync" ::: "memory")
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#define _spdk_smp_mb() spdk_mb()
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#define _spdk_ivdt_dcache(pdata)
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#elif defined(__aarch64__)
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#define _spdk_rmb() __asm volatile("dsb ld" ::: "memory")
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#define _spdk_wmb() __asm volatile("dsb st" ::: "memory")
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#define _spdk_mb() __asm volatile("dsb sy" ::: "memory")
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#define _spdk_smp_rmb() __asm volatile("dmb ishld" ::: "memory")
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#define _spdk_smp_wmb() __asm volatile("dmb ishst" ::: "memory")
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#define _spdk_smp_mb() __asm volatile("dmb ish" ::: "memory")
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#define _spdk_ivdt_dcache(pdata) asm volatile("dc civac, %0" : : "r"(pdata) : "memory");
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#elif defined(__i386__) || defined(__x86_64__)
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#define _spdk_rmb() __asm volatile("lfence" ::: "memory")
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#define _spdk_wmb() __asm volatile("sfence" ::: "memory")
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#define _spdk_mb() __asm volatile("mfence" ::: "memory")
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#define _spdk_smp_rmb() spdk_compiler_barrier()
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#define _spdk_smp_wmb() spdk_compiler_barrier()
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#if defined(__x86_64__)
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#define _spdk_smp_mb() __asm volatile("lock addl $0, -128(%%rsp); " ::: "memory");
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#elif defined(__i386__)
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#define _spdk_smp_mb() __asm volatile("lock addl $0, -128(%%esp); " ::: "memory");
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#endif
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#define _spdk_ivdt_dcache(pdata)
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#elif defined(__riscv)
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#define _spdk_rmb() __asm__ __volatile__("fence ir, ir" ::: "memory")
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#define _spdk_wmb() __asm__ __volatile__("fence ow, ow" ::: "memory")
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#define _spdk_mb() __asm__ __volatile__("fence iorw, iorw" ::: "memory")
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#define _spdk_smp_rmb() __asm__ __volatile__("fence r, r" ::: "memory")
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#define _spdk_smp_wmb() __asm__ __volatile__("fence w, w" ::: "memory")
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#define _spdk_smp_mb() __asm__ __volatile__("fence rw, rw" ::: "memory")
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#define _spdk_ivdt_dcache(pdata)
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#elif defined(__loongarch__)
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#define _spdk_rmb() __asm volatile("dbar 0" ::: "memory")
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#define _spdk_wmb() __asm volatile("dbar 0" ::: "memory")
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#define _spdk_mb() __asm volatile("dbar 0" ::: "memory")
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#define _spdk_smp_rmb() __asm volatile("dbar 0" ::: "memory")
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#define _spdk_smp_wmb() __asm volatile("dbar 0" ::: "memory")
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#define _spdk_smp_mb() __asm volatile("dbar 0" ::: "memory")
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#define _spdk_ivdt_dcache(pdata)
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#else
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#define _spdk_rmb()
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#define _spdk_wmb()
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#define _spdk_mb()
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#define _spdk_smp_rmb()
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#define _spdk_smp_wmb()
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#define _spdk_smp_mb()
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#define _spdk_ivdt_dcache(pdata)
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#error Unknown architecture
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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