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barrier: LOONGARCH memory barriers

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Implement memory barrier for LOONGARCH platforms.

Change-Id: I44f5e63e6eb3f8bf98e965a22fb86f94e727061d
Signed-off-by: Xue Liu <liuxue@loongson.cn>
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/16082
Community-CI: Mellanox Build Bot
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
This commit is contained in:
Xue Liu 2022-12-01 18:37:21 +08:00 committed by Jim Harris
parent bae7cfb49b
commit 2d686707df
1 changed files with 10 additions and 0 deletions
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10
include/spdk/barrier.h
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@ -85,6 +85,16 @@ extern "C" {
#define _spdk_smp_mb() __asm__ __volatile__("fence rw, rw" ::: "memory")
#define _spdk_ivdt_dcache(pdata)
#elif defined(__loongarch__)
#define _spdk_rmb() __asm volatile("dbar 0" ::: "memory")
#define _spdk_wmb() __asm volatile("dbar 0" ::: "memory")
#define _spdk_mb() __asm volatile("dbar 0" ::: "memory")
#define _spdk_smp_rmb() __asm volatile("dbar 0" ::: "memory")
#define _spdk_smp_wmb() __asm volatile("dbar 0" ::: "memory")
#define _spdk_smp_mb() __asm volatile("dbar 0" ::: "memory")
#define _spdk_ivdt_dcache(pdata)
#else
#define _spdk_rmb()