Group all definitions for a specific architecture
under a single #ifdef. This makes the code more
readable.
Change-Id: I4e88b9bb63f84b6275f10731aa657739ce6862e3
Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/447881
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
This follows smp_mb() implementation in the latest DPDK.
Change-Id: I39f9259a0208579034e5ff39961a2c4b8b72975c
Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-on: https://review.gerrithub.io/c/444041
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
the weak memory ordering on armv8 can be implemented using
dsb ld
see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/DMB.html
Change-Id: I4db34b87fa659967109adc688cad784018cedaae
Signed-off-by: Kefu Chai <tchaikov@gmail.com>
Reviewed-on: https://review.gerrithub.io/430767
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Suggested-by: Jonas Pfefferle
Signed-off-by: Jim Harris <james.r.harris@intel.com>
Change-Id: I33cf41d39a4546fbb5f44fccc1380c731d0224af
Reviewed-on: https://review.gerrithub.io/413705
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jonas Pfefferle <pepperjo@japf.ch>
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
These are needed in some cases on x86 where a compiler
barrier is not sufficient - for example, ensuring an
rdtsc instruction has executed before subsequent
instructions.
Signed-off-by: Jim Harris <james.r.harris@intel.com>
Change-Id: I339e2dd6138ccb11b1492e70f7c724976ef3038b
Reviewed-on: https://review.gerrithub.io/413145
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
The smp variants of memory barriers can
be used in cases where the sequential
order of loads/stores is required just
between CPU cores.
Change-Id: Ifbd187338bb441d4563672fa2f2afbe666607d76
Signed-off-by: Dariusz Stojaczyk <dariuszx.stojaczyk@intel.com>
Reviewed-on: https://review.gerrithub.io/388765
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Add code to implement the write memory barrier and read/write memory
barrier for ARM 64 platforms.
Change-Id: I8b63db25ba1f70a729874ca143db13501d976676
Signed-off-by: Barry Spinney <spinney@mellanox.com>
Reviewed-on: https://review.gerrithub.io/386534
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Prepare for the addition of more architectures by replacing the #else
case with an explicit x86 check, and add a final #else to trigger a
compile-time error if the architecture is not supported.
This adds a empty #defines of spdk_wmb() and spdk_mb() in the #else
error case so that they still show up in the generated Doxygen output.
Change-Id: Ia9e9de1648694013de1cd8a2e3edfa9b1166401c
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
Reviewed-on: https://review.gerrithub.io/386345
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Ziye Yang <optimistyzy@gmail.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
This is the first step toward isolating standard C and POSIX headers
into a single replaceable header file.
Change-Id: I527297f5e7260b01103018ad3429922962ee9add
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
spdk_compiler_barrier() prevents the compiler from moving pointer
dereferences across the barrier.
Use this in the MMIO helper functions to ensure that the compiler can't
reorder operations around e.g. hardware register access.
Specifically, this fixes the compiler optimizing out writes to
g_thread_mmio_ctrlr in the NVMe hotplug handling code.
Change-Id: I6b9cec48da0e6d8d75825c28b12ece5251110080
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
For existing \file markers, move them to the top of the header and tweak
the wording for consistency.
Change-Id: Icce748effe4dbe97d79a8c87d31caf0ee5797058
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
Also consistently place the extern "C" before any includes or other
declarations in files that already had it.
Change-Id: Ia316d5be3e509ec76c4a98cfa90ed516073351e0
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
Also add a space between Copyright and (c).
The copyright year can be determined using git metadata.
Also remove the duplicated "All rights reserved." - every instance of
this line already has a corresponding "All rights reserved" immediately
below it, except for examples/ioat/kperf/kmod/dma_perf.c, where I have
added it manually.
Performed using this command:
git ls-files | xargs sed -i -e 's/Copyright(c) \(.*\) Intel Corporation. All rights reserved./Copyright (c) Intel Corporation./'
Change-Id: I3779f404966800709024eb1eb66a50068af2716c
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
