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barrier: added spdk_smp_*mb to sync between cores

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The smp variants of memory barriers can
be used in cases where the sequential
order of loads/stores is required just
between CPU cores.

Change-Id: Ifbd187338bb441d4563672fa2f2afbe666607d76
Signed-off-by: Dariusz Stojaczyk <dariuszx.stojaczyk@intel.com>
Reviewed-on: https://review.gerrithub.io/388765
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
This commit is contained in:
Dariusz Stojaczyk 2017-11-23 13:35:15 +01:00 committed by Jim Harris
parent 3b2ed0e968
commit 962fdadfb8
1 changed files with 36 additions and 0 deletions
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36
include/spdk/barrier.h
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@ -72,6 +72,42 @@ extern "C" {
#error Unknown architecture
#endif
/** SMP read memory barrier. */
#ifdef __PPC64__
#define spdk_smp_rmb() __asm volatile("lwsync" ::: "memory")
#elif defined(__aarch64__)
#define spdk_smp_rmb() __asm volatile("dmb ishld" ::: "memory")
#elif defined(__i386__) || defined(__x86_64__)
#define spdk_smp_rmb() spdk_compiler_barrier()
#else
#define spdk_smp_rmb()
#error Unknown architecture
#endif
/** SMP write memory barrier. */
#ifdef __PPC64__
#define spdk_smp_wmb() __asm volatile("lwsync" ::: "memory")
#elif defined(__aarch64__)
#define spdk_smp_wmb() __asm volatile("dmb ishst" ::: "memory")
#elif defined(__i386__) || defined(__x86_64__)
#define spdk_smp_wmb() spdk_compiler_barrier()
#else
#define spdk_smp_wmb()
#error Unknown architecture
#endif
/** SMP read/write memory barrier. */
#ifdef __PPC64__
#define spdk_smp_mb() spdk_mb()
#elif defined(__aarch64__)
#define spdk_smp_mb() __asm volatile("dmb ish" ::: "memory")
#elif defined(__i386__) || defined(__x86_64__)
#define spdk_smp_mb() spdk_mb()
#else
#define spdk_smp_mb()
#error Unknown architecture
#endif
#ifdef __cplusplus
}
#endif