barrier: RISC-V memory barriers
Introduce memory barriers for RISC-V. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Change-Id: I6761c2b6ddc28a856cac1e1a67e0b0fa0e0ab3a0 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12878 Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
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@ -103,6 +103,16 @@ extern "C" {
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#endif
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#define _spdk_ivdt_dcache(pdata)
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#elif defined(__riscv)
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#define _spdk_rmb() __asm__ __volatile__("fence ir, ir" ::: "memory")
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#define _spdk_wmb() __asm__ __volatile__("fence ow, ow" ::: "memory")
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#define _spdk_mb() __asm__ __volatile__("fence iorw, iorw" ::: "memory")
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#define _spdk_smp_rmb() __asm__ __volatile__("fence r, r" ::: "memory")
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#define _spdk_smp_wmb() __asm__ __volatile__("fence w, w" ::: "memory")
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#define _spdk_smp_mb() __asm__ __volatile__("fence rw, rw" ::: "memory")
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#define _spdk_ivdt_dcache(pdata)
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#else
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#define _spdk_rmb()
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