From c1e0b73e85105db15172362dffd9e2d778f57504 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: Thu, 2 Jun 2022 13:46:28 +0200
Subject: [PATCH] barrier: RISC-V memory barriers

Introduce memory barriers for RISC-V.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Change-Id: I6761c2b6ddc28a856cac1e1a67e0b0fa0e0ab3a0
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12878
Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
Community-CI: Mellanox Build Bot
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com>
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
---
 include/spdk/barrier.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/spdk/barrier.h b/include/spdk/barrier.h
index eb1992ba2..5b13381ac 100644
--- a/include/spdk/barrier.h
+++ b/include/spdk/barrier.h
@@ -103,6 +103,16 @@ extern "C" {
 #endif
 #define _spdk_ivdt_dcache(pdata)
 
+#elif defined(__riscv)
+
+#define _spdk_rmb()	__asm__ __volatile__("fence ir, ir" ::: "memory")
+#define _spdk_wmb()	__asm__ __volatile__("fence ow, ow" ::: "memory")
+#define _spdk_mb()	__asm__ __volatile__("fence iorw, iorw" ::: "memory")
+#define _spdk_smp_rmb()	__asm__ __volatile__("fence r, r" ::: "memory")
+#define _spdk_smp_wmb()	__asm__ __volatile__("fence w, w" ::: "memory")
+#define _spdk_smp_mb()	__asm__ __volatile__("fence rw, rw" ::: "memory")
+#define _spdk_ivdt_dcache(pdata)
+
 #else
 
 #define _spdk_rmb()