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nvme: add memory barrier in completion path for arm64

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Add a memory barrier for arm64 to prevent possible reordering
of tracker and cpl access,
because arm64 has less strict memory ordering behavior than x86.

Change-Id: I0a8716f7bfeffb0bbce27ee3174e214c8e4566b4
Signed-off-by: heyang <heyang18@huawei.com>
Reviewed-on: https://review.gerrithub.io/c/442964
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
This commit is contained in:
heyang 2019-02-01 14:33:19 +08:00 committed by Jim Harris
parent 80ff32cfcc
commit 7cd3a6f5e0
1 changed files with 1 additions and 1 deletions
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2
lib/nvme/nvme_pcie.c
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@ -2076,7 +2076,7 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
if (cpl->status.p != pqpair->phase) {
break;
}
#ifdef __PPC64__
#if defined(__PPC64__) || defined(__aarch64__)
/*
* This memory barrier prevents reordering of:
* - load after store from/to tr