From 7cd3a6f5e061eac76515e82d61714ba56cc3c4f5 Mon Sep 17 00:00:00 2001
From: heyang <heyang18@huawei.com>
Date: Fri, 1 Feb 2019 14:33:19 +0800
Subject: [PATCH] nvme: add memory barrier in completion path for arm64

Add a memory barrier for arm64 to prevent possible reordering
of tracker and cpl access,
because arm64 has less strict memory ordering behavior than x86.

Change-Id: I0a8716f7bfeffb0bbce27ee3174e214c8e4566b4
Signed-off-by: heyang <heyang18@huawei.com>
Reviewed-on: https://review.gerrithub.io/c/442964
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
---
 lib/nvme/nvme_pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/nvme/nvme_pcie.c b/lib/nvme/nvme_pcie.c
index a30c9a00a..eba6f3b69 100644
--- a/lib/nvme/nvme_pcie.c
+++ b/lib/nvme/nvme_pcie.c
@@ -2076,7 +2076,7 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
 		if (cpl->status.p != pqpair->phase) {
 			break;
 		}
-#ifdef __PPC64__
+#if defined(__PPC64__) || defined(__aarch64__)
 		/*
 		 * This memory barrier prevents reordering of:
 		 * - load after store from/to tr