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doc: correct explanation of NVMe SQ command submission

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Correct explanation of NVMe SQ command submission

Change-Id: Ibdb3d13369c916708269c18fc04d5680044fce8e
Signed-off-by: Michael Bang <mi.bang@samsung.com>
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6027
Community-CI: Mellanox Build Bot
Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
Reviewed-by: sunshihao <sunshihao@huawei.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com>
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
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Michael Bang 2021-01-21 12:52:21 +01:00 committed by Tomasz Zawadzki
parent 43c2070171
commit 75440d0537
1 changed files with 2 additions and 2 deletions
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doc/nvme_spec.md
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@ -20,8 +20,8 @@ registers involved that are called doorbells.
An I/O is submitted to an NVMe device by constructing a 64 byte command, placing
it into the submission queue at the current location of the submission queue
head index, and then writing the new index of the submission queue head to the
submission queue head doorbell register. It's actually valid to copy a whole set
tail index, and then writing the new index of the submission queue tail to the
submission queue tail doorbell register. It's actually valid to copy a whole set
of commands into open slots in the ring and then write the doorbell just one
time to submit the whole batch.