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nvme/pcie: memory barrier for RISC-V

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Play it safe and add the same memory barrier in
nvme_pcie_qpair_process_completions() as for ppc64.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Change-Id: I7079b4769d30106387ef4549495a72b7fea6a77a
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12879
Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
Community-CI: Mellanox Build Bot
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com>
This commit is contained in:
Heinrich Schuchardt 2022-06-02 14:58:44 +02:00 committed by Tomasz Zawadzki
parent c1e0b73e85
commit 72b5626d33
1 changed files with 1 additions and 1 deletions
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2
lib/nvme/nvme_pcie_common.c
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@ -932,7 +932,7 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
__builtin_prefetch(&pqpair->tr[next_cpl->cid]);
}
#ifdef __PPC64__
#if defined(__PPC64__) || defined(__riscv)
/*
* This memory barrier prevents reordering of:
* - load after store from/to tr