From 72b5626d3351666e0f14025dce76b48c554deb5c Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: Thu, 2 Jun 2022 14:58:44 +0200
Subject: [PATCH] nvme/pcie: memory barrier for RISC-V

Play it safe and add the same memory barrier in
nvme_pcie_qpair_process_completions() as for ppc64.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Change-Id: I7079b4769d30106387ef4549495a72b7fea6a77a
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12879
Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
Community-CI: Mellanox Build Bot
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com>
---
 lib/nvme/nvme_pcie_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/nvme/nvme_pcie_common.c b/lib/nvme/nvme_pcie_common.c
index a63f1df65..8ddecc384 100644
--- a/lib/nvme/nvme_pcie_common.c
+++ b/lib/nvme/nvme_pcie_common.c
@@ -932,7 +932,7 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
 			__builtin_prefetch(&pqpair->tr[next_cpl->cid]);
 		}
 
-#ifdef __PPC64__
+#if defined(__PPC64__) || defined(__riscv)
 		/*
 		 * This memory barrier prevents reordering of:
 		 * - load after store from/to tr