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Spdk/include/spdk/pci_ids.h

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Replace most BSD 3-clause license text with SPDX identifier. Many open source projects have moved to using SPDX identifiers to specify license information, reducing the amount of boilerplate code in every source file. This patch replaces the bulk of SPDK .c, .cpp and Makefiles with the BSD-3-Clause identifier. Almost all of these files share the exact same license text, and this patch only modifies the files that contain the most common license text. There can be slight variations because the third clause contains company names - most say "Intel Corporation", but there are instances for Nvidia, Samsung, Eideticom and even "the copyright holder". Used a bash script to automate replacement of the license text with SPDX identifier which is checked into scripts/spdx.sh. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Iaa88ab5e92ea471691dc298cfe41ebfb5d169780 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12904 Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Dong Yi <dongx.yi@intel.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Reviewed-by: Paul Luse <paul.e.luse@intel.com> Reviewed-by: <qun.wan@intel.com>
2022-06-03 19:15:11 +00:00
/* SPDX-License-Identifier: BSD-3-Clause
Remove year from copyright headers. Also add a space between Copyright and (c). The copyright year can be determined using git metadata. Also remove the duplicated "All rights reserved." - every instance of this line already has a corresponding "All rights reserved" immediately below it, except for examples/ioat/kperf/kmod/dma_perf.c, where I have added it manually. Performed using this command: git ls-files | xargs sed -i -e 's/Copyright(c) \(.*\) Intel Corporation. All rights reserved./Copyright (c) Intel Corporation./' Change-Id: I3779f404966800709024eb1eb66a50068af2716c Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-01-26 17:47:22 +00:00
* Copyright (c) Intel Corporation.
NVMe: Add public API to get log pages. 1 Add supported log pages data structure. 2 Bulid up supported log pages when NVME start. 3 Provide unified API for getting log pages. 3 Unit test suit optimization base on above modification. Change-Id: I03cdb93f5c94e6897510d7f19bc7d9f4e70f9222 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-06 05:43:33 +00:00
* All rights reserved.
*/
doc: add Doxygen file marker to all public headers For existing \file markers, move them to the top of the header and tweak the wording for consistency. Change-Id: Icce748effe4dbe97d79a8c87d31caf0ee5797058 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-04-29 18:04:33 +00:00
/** \file
* PCI device ID list
*/
pci_ids: add SPDK_ prefix PCI_VENDOR_ID_INTEL -> SPDK_PCI_VID_INTEL Also change the inclusion guard macro to be consistent with the other SPDK headers. Change-Id: I29346267172cb8c07cc4289eed4eca2d55e942d6 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-02-08 21:08:06 +00:00
#ifndef SPDK_PCI_IDS
#define SPDK_PCI_IDS
NVMe: Add public API to get log pages. 1 Add supported log pages data structure. 2 Bulid up supported log pages when NVME start. 3 Provide unified API for getting log pages. 3 Unit test suit optimization base on above modification. Change-Id: I03cdb93f5c94e6897510d7f19bc7d9f4e70f9222 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-06 05:43:33 +00:00
include: move standard includes into spdk/stdinc.h This is the first step toward isolating standard C and POSIX headers into a single replaceable header file. Change-Id: I527297f5e7260b01103018ad3429922962ee9add Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2017-05-01 20:22:48 +00:00
#include "spdk/stdinc.h"
Add extern "C" wrapper to all public headers Also consistently place the extern "C" before any includes or other declarations in files that already had it. Change-Id: Ia316d5be3e509ec76c4a98cfa90ed516073351e0 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-02-12 14:52:35 +00:00
#ifdef __cplusplus
extern "C" {
#endif
nvme: change nvme_intel.c to nvme_quirks.c Make the quirks mechanism generic in preparation for quirks for devices from other vendors. Change-Id: Ic003b020a38f1b966021db30e3f2bce9cf6a1a0d Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-10-24 23:29:47 +00:00
#define SPDK_PCI_ANY_ID 0xffff
pci_ids: add SPDK_ prefix PCI_VENDOR_ID_INTEL -> SPDK_PCI_VID_INTEL Also change the inclusion guard macro to be consistent with the other SPDK headers. Change-Id: I29346267172cb8c07cc4289eed4eca2d55e942d6 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-02-08 21:08:06 +00:00
#define SPDK_PCI_VID_INTEL 0x8086
nvme: add quirk to delay checking device readiness (#56)
2016-10-27 06:34:32 +00:00
#define SPDK_PCI_VID_MEMBLAZE 0x1c5f
nvme: add chk_rdy quirk for some Samsung drives Add some known Samsung controllers to those requiring the quirk, NVME_QUIRK_DELAY_BEFORE_CHK_RDY. Addresses an issue for those who may not have later firmware that corrects the problem. Correspondingly, extend the delay from 2 secs to 2.5 secs. Change-Id: Iee773905a2a49711775042c061f6c347e0da85e9 Signed-off-by: Lance Hartmann <lance.hartmann@oracle.com> Reviewed-on: https://review.gerrithub.io/419273 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
2018-07-13 18:20:21 +00:00
#define SPDK_PCI_VID_SAMSUNG 0x144d
nvme: add NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC The VirtualBox emulated NVMe device will intermittently hang on the first read/write command after an I/O qpair has been allocated. The frequency of the hang diminishes if a delay is added after allocating the I/O qpair - until it disappears completely with a 100us delay. So add a quirk to insert this delay. Note - the 100us delay was tested by running the hello_world example app 50000 times. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I237e31b1b8a1a1e28262851ae0a21cd7345f0f1a
2017-04-29 19:21:32 +00:00
#define SPDK_PCI_VID_VIRTUALBOX 0x80ee
env: add pci_virtio.c This patch only adds the pci_virtio.c file, without changing any functionality. This is required for future rte_virtio migration to SPDK. Change-Id: I7774cdfdaf8934fde588e25b5db5dd86a9cbfb3f Signed-off-by: Dariusz Stojaczyk <dariuszx.stojaczyk@intel.com> Reviewed-on: https://review.gerrithub.io/379484 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2017-09-21 15:11:06 +00:00
#define SPDK_PCI_VID_VIRTIO 0x1af4
nvme: add a quirk for identify 0x2 Change-Id: I9cfc237a8514a1d323313851e14576ba2ba69077 Signed-off-by: Young Tack Jin <youngtack.jin@circuitblvd.com> Reviewed-on: https://review.gerrithub.io/410529 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2018-05-09 01:41:46 +00:00
#define SPDK_PCI_VID_CNEXLABS 0x1d1d
nvme: add SHST_COMPLETE quirk for VMWare emulated SSDs VMWare Workstation NVMe emulation does not seem to write the SHST_COMPLETE bit within 10 seconds, resulting in an ERRLOG during detach/shutdown. So add a quirk to cover these VMWare SSDs. But rather than squashing the ERRLOG completely for these SSDs, just add a message instead indicating this is somewhat expected on these VMWare emulated SSDs. Fixes issue #676. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I3dfcb631feda639926fd712f1f41abb66cbf2096 Reviewed-on: https://review.gerrithub.io/c/445942 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
2019-02-22 12:51:32 +00:00
#define SPDK_PCI_VID_VMWARE 0x15ad
nvme: add quirks for new RedHat QEMU NVMe dev/vendor ID QEMU 6.0 by default uses a RedHat dev/vendor ID rather than the Intel one that has always been used to date. We need the NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH quirk so that we do not use wide instructions to copy SQEs to a virtualized CMB, since QEMU does not support that. The NVME_INTEL_QUIRK_NO_LOG_PAGES quirk is only needed for devices with SPDK_PCI_VID_INTEL, so we do not need to carry this one over to the new REDHAT entry. Fixes issue #1986. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I3d339b3525e7c6ceb792eb9d143e7a922c19344d Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/8226 Reviewed-by: Paul Luse <paul.e.luse@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2021-06-09 17:00:45 +00:00
#define SPDK_PCI_VID_REDHAT 0x1b36
nvmf/vfio-user: define SPDK_PCI_VID_NUTANIX macro and use it in vfio-user Change-Id: I09820f484be3e962bcc4e80964d152e64957b331 Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/10550 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2021-12-06 09:53:41 +00:00
#define SPDK_PCI_VID_NUTANIX 0x4e58
nvme/quirks: don't use SGL for Huawei SSDs We see reports that Huawei SSDs can't handle hardware SGL properly, it requires additional alignment, so add a quirk here to force Huawei SSDs use PRP instead. Fix #2489. Change-Id: I20a57e754bc6ff8666d681191994818f2192decc Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12405 Community-CI: Mellanox Build Bot Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: wanghailiang <hailiangx.e.wang@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com> Reviewed-by: GangCao <gang.cao@intel.com> Reviewed-by: Dong Yi <dongx.yi@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2022-04-28 05:20:45 +00:00
#define SPDK_PCI_VID_HUAWEI 0x19e5
nvme: add admin queue size quirk for Hyper-V Hyper-V NVMe SSD controllers require admin queue size to be even multiples of a page. Add quirk to adjust the admin queue size if user overrides the default value to something other than an even multiple. As part of this change, set the quirks earlier when constructing a pcie controller, so that the quirks value can be used in the generic nvme_ctrlr_construct() function. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I417cd3cdc7e3ba512ec412f4876b0e0b7432341c Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/14220 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Reviewed-by: Aleksey Marchuk <alexeymar@nvidia.com>
2022-08-25 17:53:20 +00:00
#define SPDK_PCI_VID_MICROSOFT 0x1414
nvme: Add Intel NVMe device supported feature quirks This patch adds Intel NVMe device list and overrides the supported log pages according to the quirk list. In particular, the READ_CMD_LATENCY and WRITE_CMD_LATENCY pages are supported on Intel DC P3x00 devices despite not being listed in the Intel vendor-specific log page directory. Change-Id: I3a2b6a5fa142c6e9c93567df65e85980bd3c7cc0 Signed-off-by: Cunyin Chang <cunyin.chang@intel.com>
2016-01-27 07:08:53 +00:00
env: add spdk_pci_id->class_id This follows struct rte_pci_id which had class_id as well. We'll need it to make some additional DPDK APIs public through the env abstraction. Change-Id: I794a6cd6b17e48daf53b48fa5abe3d3dcfeaa403 Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3182 Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-07-02 21:17:30 +00:00
#define SPDK_PCI_CLASS_ANY_ID 0xffffff
nvme: move class code to pci_ids.h Move toward collecting PCI IDs, class codes, etc. in pci_ids.h instead of individual device-specific headers. Change-Id: Icff162d48ac663db71d0576ceee16a9bd7a751cd Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-02-09 16:31:09 +00:00
/**
* PCI class code for NVMe devices.
*
* Base class code 01h: mass storage
* Subclass code 08h: non-volatile memory
* Programming interface 02h: NVM Express
*/
#define SPDK_PCI_CLASS_NVME 0x010802
include/env: update PCI ID names from IDXD->DSA In prep for adding IAA support Signed-off-by: paul luse <paul.e.luse@intel.com> Change-Id: I7eed173f9f907aa1c010d12db87b8dc27cd7495b Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12760 Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2022-05-20 15:59:23 +00:00
#define PCI_DEVICE_ID_INTEL_DSA 0x0b25
pci/accel/idxd: add PCI IDs for IAA device Intel Analytics Accelerator, this is the start of the patches to add this support to accel_fw. Signed-off-by: paul luse <paul.e.luse@intel.com> Change-Id: I7410710697d2947355181616b35cc8ab78bbddfe Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/11985 Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2022-03-18 16:05:40 +00:00
#define PCI_DEVICE_ID_INTEL_IAA 0x0cfe
lib/idxd: add low level idxd library Module, etc., will follow. Notes: * IDXD is an Intel silicon feature available in future Intel CPUs. Initial development is being done on a simulator. Once HW is available and the code fully tested the experimental label will be lifted. Spec can be found here: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification * The current implementation will only work with VFIO. * DSA has a number of engines that can be grouped based on application need such as type of memory being served or QoS. Engines are processing units and are assigned to groups. Work queues are on device structures that act as front-end groups for queueing descriptors. Full details on what is configurable & how will come in later doc patches. * There is a finite number of work queue slots that are divided amongst the number of desired work queues in some fashion (ie evenly). * SW (outside of the idxd lib) is required to manage flow control, to not over-run the work queues.This is provided in the accel plug-in module. The upper layers use public API to manage this. * Work queue submissions are done with a 64 byte atomic instruction * The design here creates a set of descriptor rings per channel that match the size of the work queues. Then, an spdk_bit_array is used to make sure we don't overrun a queue. If there are not slots available, the operation is put on a linked list to be retried later from the poller. * As we need to support any number of channels (we can't limit ourselves to the number of work queues) we need to dynamically size/resize our per channel descriptor rings based on the number of current channels. This is done from upper layers via public API into the lib. * As channels are created, the total number of work queue slots is divided across the channels evenly. Same thing when they are destroyed, remaining channels with see the ring sizes increase. This is done from upper layers via public API into the lib. * The sim has 64 total work queue entries (WQE) that get dolled out to the work queues (WQ) evenly. Signed-off-by: paul luse <paul.e.luse@intel.com> Change-Id: I899bbeda3cef3db05bea4197b8757e89dddb579d Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/1809 Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Vitaliy Mysak <vitaliy.mysak@intel.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2020-04-10 15:29:01 +00:00
Drop libpciaccess and switch to DPDK PCI This patch also drops support for automatically unbinding devices from the kernel - run scripts/setup.sh first. Our generic pci interface is now hidden behind include/spdk/pci.h and implemented in lib/util/pci.c. We no longer wrap the calls in nvme_impl.h or ioat_impl.h. The implementation now only uses DPDK and the libpciaccess dependency has been removed. If using a version of DPDK earlier than 16.07, enumerating devices by class code isn't available and only Intel SSDs will be discovered. DPDK 16.07 adds enumeration by class code and all NVMe devices will be correctly discovered. Change-Id: I0e8bac36b5ca57df604a2b310c47342c67dc9f3c Signed-off-by: Ben Walker <benjamin.walker@intel.com>
2016-08-08 22:57:49 +00:00
#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20
#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21
#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22
#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23
#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24
#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25
#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26
#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
#define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
#define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
#define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
#define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
#define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
#define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
#define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
#define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
#define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
#define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
#define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
#define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
#define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
#define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
#define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
#define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
#define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
#define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
#define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
#define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
#define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50
#define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51
#define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52
#define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53
#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
#define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20
#define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21
#define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22
#define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23
#define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24
#define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25
#define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26
#define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27
#define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e
#define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f
ioat: add Skylake Xeon device ID There is only a single device ID for all channels on the SKX implementation of I/OAT. Change-Id: I90ee79b1b673a199754f1ca4c9e38e934294e261 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2017-01-18 18:15:50 +00:00
#define PCI_DEVICE_ID_INTEL_IOAT_SKX 0x2021
ioat: add device IDs for new CB-DMA engines Icelake SP Xeon and Snowridge Xeon-D will share the same IOAT (CB-DMA) PCI device ID. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: Ia2da3a0923c4db73db5d224a3db4f6913e7e1891 Reviewed-on: https://review.gerrithub.io/c/446157 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
2019-02-13 18:15:45 +00:00
#define PCI_DEVICE_ID_INTEL_IOAT_ICX 0x0b00
env: add the device ID of virtio device From the QEMU doc: 1af4:1000 network device (legacy) 1af4:1001 block device (legacy) 1af4:1002 balloon device (legacy) 1af4:1003 console device (legacy) 1af4:1004 SCSI host bus adapter device (legacy) 1af4:1005 entropy generator device (legacy) 1af4:1009 9p filesystem device (legacy) 1af4:1041 network device (modern) 1af4:1042 block device (modern) 1af4:1043 console device (modern) 1af4:1044 entropy generator device (modern) 1af4:1045 balloon device (modern) 1af4:1048 SCSI host bus adapter device (modern) 1af4:1049 9p filesystem device (modern) 1af4:1050 virtio gpu device (modern) 1af4:1052 virtio input device (modern) Change-Id: I75b04c331aebae9f20fecbca85d64415114ae5ff Signed-off-by: Jin Yu <jin.yu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/2369 Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com>
2020-05-11 17:19:32 +00:00
#define PCI_DEVICE_ID_VIRTIO_BLK_LEGACY 0x1001
#define PCI_DEVICE_ID_VIRTIO_SCSI_LEGACY 0x1004
#define PCI_DEVICE_ID_VIRTIO_BLK_MODERN 0x1042
#define PCI_DEVICE_ID_VIRTIO_SCSI_MODERN 0x1048
pci_ids: add virtio-vhost-user device id Add the virtio-vhost-user device id in the list of virtio devices so that the setup script can handle this device too. Change-Id: I203ce75a2561bcdfbe2301df0679090678d7d530 Signed-off-by: Nikos Dragazis <ndragazis@arrikto.com> Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/441055 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
2019-01-05 23:49:27 +00:00
#define PCI_DEVICE_ID_VIRTIO_VHOST_USER 0x1017
env: add pci_virtio.c This patch only adds the pci_virtio.c file, without changing any functionality. This is required for future rte_virtio migration to SPDK. Change-Id: I7774cdfdaf8934fde588e25b5db5dd86a9cbfb3f Signed-off-by: Dariusz Stojaczyk <dariuszx.stojaczyk@intel.com> Reviewed-on: https://review.gerrithub.io/379484 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
2017-09-21 15:11:06 +00:00
vmd: update for changes in IceLake platform Add the new device ID for VMD devices so VMD devices can be unbound and used with the SPDK setup script. Bus numbering for VMD devices is different on IceLake platforms, and only half of the bus numbers are available. Add a function to set the starting bus number and the max bus number by reading the new BUS_RESTRICT_CAP and BUS_RESTRICTIONS VMD registers. Signed-off-by: Sydney Vanda <sydney.m.vanda@intel.com> Change-Id: I8905d4bcba84c74e3dadfb27262e668c4281b0c8 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/8331 Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ziye Yang <ziye.yang@intel.com> Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2021-06-14 20:06:35 +00:00
#define PCI_DEVICE_ID_INTEL_VMD_SKX 0x201d
#define PCI_DEVICE_ID_INTEL_VMD_ICX 0x28c0
#define PCI_ROOT_PORT_A_INTEL_SKX 0x2030
#define PCI_ROOT_PORT_B_INTEL_SKX 0x2031
#define PCI_ROOT_PORT_C_INTEL_SKX 0x2032
#define PCI_ROOT_PORT_D_INTEL_SKX 0x2033
#define PCI_ROOT_PORT_A_INTEL_ICX 0x347a
#define PCI_ROOT_PORT_B_INTEL_ICX 0x347b
#define PCI_ROOT_PORT_C_INTEL_ICX 0x347c
#define PCI_ROOT_PORT_D_INTEL_ICX 0x347d
lib/env_dpdk: Added VMD PCI driver object This patch add support for VMD driver object. New PCI device ID for VMD device was added. Change-Id: I47bd8772a15ad370a14b7cc9460a177c91e6dd6a Signed-off-by: Wojciech Malikowski <wojciech.malikowski@intel.com> Signed-off-by: Orden Smith <orden.e.smith@intel.com> Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/455545 Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
2019-05-23 14:51:03 +00:00
Add extern "C" wrapper to all public headers Also consistently place the extern "C" before any includes or other declarations in files that already had it. Change-Id: Ia316d5be3e509ec76c4a98cfa90ed516073351e0 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-02-12 14:52:35 +00:00
#ifdef __cplusplus
}
#endif
pci_ids: add SPDK_ prefix PCI_VENDOR_ID_INTEL -> SPDK_PCI_VID_INTEL Also change the inclusion guard macro to be consistent with the other SPDK headers. Change-Id: I29346267172cb8c07cc4289eed4eca2d55e942d6 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2016-02-08 21:08:06 +00:00
#endif /* SPDK_PCI_IDS */
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