fed358a0e7
The following error was reported when running gpt_ut which is related to crc32_update(). "load of misaligned address 0x001ffeff78cc for type 'const uint64_t', which requires 8 byte alignment". This patch preprocesses the first several bytes to make the buf address passed to __crc32_d or__crc32_cd is 8 byte aligned. And finally process the trailing bytes. For function spdk_crc32c_update in crc32c.c, memcpy was used to avoid misaligned load problem. Update it with above solution to reduce extra overhead. Signed-off-by: Richael Zhuang <richael.zhuang@arm.com> Change-Id: I7c7aaa41e1c042a96668158818b06729fb3ceec6 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/16801 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
128 lines
2.7 KiB
C
128 lines
2.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2017 Intel Corporation.
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* All rights reserved.
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*/
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#include "util_internal.h"
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#include "crc_internal.h"
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#include "spdk/crc32.h"
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#ifdef SPDK_HAVE_ISAL
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uint32_t
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spdk_crc32c_update(const void *buf, size_t len, uint32_t crc)
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{
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return crc32_iscsi((unsigned char *)buf, len, crc);
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}
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#elif defined(SPDK_HAVE_SSE4_2)
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uint32_t
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spdk_crc32c_update(const void *buf, size_t len, uint32_t crc)
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{
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size_t count_pre, count_post, count_mid;
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const uint64_t *dword_buf;
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uint64_t crc_tmp64;
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/* process the head and tail bytes seperately to make the buf address
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* passed to _mm_crc32_u64 is 8 byte aligned. This can avoid unaligned loads.
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*/
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count_pre = ((uint64_t)buf & 7) == 0 ? 0 : 8 - ((uint64_t)buf & 7);
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count_post = (uint64_t)(buf + len) & 7;
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count_mid = (len - count_pre - count_post) / 8;
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while (count_pre--) {
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crc = _mm_crc32_u8(crc, *(const uint8_t *)buf);
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buf++;
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}
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/* _mm_crc32_u64() needs a 64-bit intermediate value */
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crc_tmp64 = crc;
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dword_buf = (const uint64_t *)buf;
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while (count_mid--) {
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crc_tmp64 = _mm_crc32_u64(crc_tmp64, *dword_buf);
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dword_buf++;
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}
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buf = dword_buf;
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crc = (uint32_t)crc_tmp64;
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while (count_post--) {
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crc = _mm_crc32_u8(crc, *(const uint8_t *)buf);
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buf++;
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}
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return crc;
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}
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#elif defined(SPDK_HAVE_ARM_CRC)
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uint32_t
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spdk_crc32c_update(const void *buf, size_t len, uint32_t crc)
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{
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size_t count_pre, count_post, count_mid;
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const uint64_t *dword_buf;
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/* process the head and tail bytes seperately to make the buf address
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* passed to crc32_cd is 8 byte aligned. This can avoid unaligned loads.
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*/
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count_pre = ((uint64_t)buf & 7) == 0 ? 0 : 8 - ((uint64_t)buf & 7);
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count_post = (uint64_t)(buf + len) & 7;
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count_mid = (len - count_pre - count_post) / 8;
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while (count_pre--) {
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crc = __crc32cb(crc, *(const uint8_t *)buf);
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buf++;
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}
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dword_buf = (const uint64_t *)buf;
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while (count_mid--) {
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crc = __crc32cd(crc, *dword_buf);
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dword_buf++;
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}
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buf = dword_buf;
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while (count_post--) {
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crc = __crc32cb(crc, *(const uint8_t *)buf);
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buf++;
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}
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return crc;
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}
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#else /* Neither SSE 4.2 nor ARM CRC32 instructions available */
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static struct spdk_crc32_table g_crc32c_table;
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__attribute__((constructor)) static void
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crc32c_init(void)
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{
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crc32_table_init(&g_crc32c_table, SPDK_CRC32C_POLYNOMIAL_REFLECT);
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}
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uint32_t
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spdk_crc32c_update(const void *buf, size_t len, uint32_t crc)
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{
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return crc32_update(&g_crc32c_table, buf, len, crc);
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}
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#endif
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uint32_t
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spdk_crc32c_iov_update(struct iovec *iov, int iovcnt, uint32_t crc32c)
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{
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int i;
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if (iov == NULL) {
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return crc32c;
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}
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for (i = 0; i < iovcnt; i++) {
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assert(iov[i].iov_base != NULL);
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assert(iov[i].iov_len != 0);
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crc32c = spdk_crc32c_update(iov[i].iov_base, iov[i].iov_len, crc32c);
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}
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return crc32c;
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}
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