0b7138e97f
Per specification. Signed-off-by: paul luse <paul.e.luse@intel.com> Change-Id: Ic93349c7d3ed50fa6e502e39db0347141804d4c4 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/15673 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
163 lines
3.7 KiB
C
163 lines
3.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2020 Intel Corporation.
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* All rights reserved.
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*/
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#ifndef __IDXD_H__
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#define __IDXD_H__
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#include "spdk/stdinc.h"
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#include "spdk/idxd.h"
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#include "spdk/queue.h"
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#include "spdk/mmio.h"
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#include "spdk/idxd_spec.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* TODO: get the gcc intrinsic to work. */
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#define nop() asm volatile ("nop")
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static inline void movdir64b(void *dst, const void *src)
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{
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asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02"
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: "=m"(*(char *)dst)
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: "d"(src), "a"(dst));
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}
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#define IDXD_REGISTER_TIMEOUT_US 50
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#define IDXD_DRAIN_TIMEOUT_US 500000
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#define WQ_MODE_DEDICATED 1
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/* TODO: consider setting the max per batch limit via RPC. */
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/* The following sets up a max desc count per batch of 32 */
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#define LOG2_WQ_MAX_BATCH 5 /* 2^5 = 32 */
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#define DESC_PER_BATCH (1 << LOG2_WQ_MAX_BATCH)
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#define LOG2_WQ_MAX_XFER 30 /* 2^30 = 1073741824 */
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#define WQ_PRIORITY_1 1
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#define IDXD_MAX_QUEUES 64
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enum idxd_dev {
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IDXD_DEV_TYPE_DSA = 0,
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IDXD_DEV_TYPE_IAA = 1,
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};
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/* Each pre-allocated batch structure goes on a per channel list and
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* contains the memory for both user descriptors.
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*/
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struct idxd_batch {
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struct idxd_hw_desc *user_desc;
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struct idxd_ops *user_ops;
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uint64_t user_desc_addr;
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uint8_t index;
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uint8_t refcnt;
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struct spdk_idxd_io_channel *chan;
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TAILQ_ENTRY(idxd_batch) link;
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};
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struct device_config {
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uint8_t config_num;
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uint8_t num_groups;
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uint16_t total_wqs;
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uint16_t total_engines;
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};
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struct idxd_ops;
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struct spdk_idxd_io_channel {
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struct spdk_idxd_device *idxd;
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/* The portal is the address that we write descriptors to for submission. */
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void *portal;
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uint32_t portal_offset;
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bool pasid_enabled;
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/* The currently open batch */
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struct idxd_batch *batch;
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/*
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* User descriptors (those included in a batch) are managed independently from
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* data descriptors and are located in the batch structure.
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*/
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void *desc_base;
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STAILQ_HEAD(, idxd_ops) ops_pool;
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/* Current list of outstanding operations to poll. */
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STAILQ_HEAD(op_head, idxd_ops) ops_outstanding;
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void *ops_base;
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TAILQ_HEAD(, idxd_batch) batch_pool;
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void *batch_base;
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};
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struct pci_dev_id {
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int vendor_id;
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int device_id;
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};
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/*
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* This struct wraps the hardware completion record which is 32 bytes in
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* size and must be 32 byte aligned.
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*/
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struct idxd_ops {
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union {
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struct dsa_hw_comp_record hw;
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struct iaa_hw_comp_record iaa_hw;
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};
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void *cb_arg;
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spdk_idxd_req_cb cb_fn;
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struct idxd_batch *batch;
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struct idxd_hw_desc *desc;
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union {
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uint32_t *crc_dst;
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uint32_t *output_size;
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};
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struct idxd_ops *parent;
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uint32_t count;
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STAILQ_ENTRY(idxd_ops) link;
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};
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SPDK_STATIC_ASSERT(sizeof(struct idxd_ops) == 128, "size mismatch");
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struct spdk_idxd_impl {
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const char *name;
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int (*probe)(void *cb_ctx, spdk_idxd_attach_cb attach_cb,
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spdk_idxd_probe_cb probe_cb);
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void (*destruct)(struct spdk_idxd_device *idxd);
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void (*dump_sw_error)(struct spdk_idxd_device *idxd, void *portal);
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char *(*portal_get_addr)(struct spdk_idxd_device *idxd);
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STAILQ_ENTRY(spdk_idxd_impl) link;
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};
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struct spdk_idxd_device {
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struct spdk_idxd_impl *impl;
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void *portal;
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uint32_t socket_id;
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uint32_t num_channels;
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uint32_t total_wq_size;
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uint32_t chan_per_device;
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pthread_mutex_t num_channels_lock;
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bool pasid_enabled;
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enum idxd_dev type;
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struct iaa_aecs *aecs;
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uint64_t aecs_addr;
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uint32_t version;
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};
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void idxd_impl_register(struct spdk_idxd_impl *impl);
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#define SPDK_IDXD_IMPL_REGISTER(name, impl) \
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static void __attribute__((constructor)) idxd_impl_register_##name(void) \
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{ \
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idxd_impl_register(impl); \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __IDXD_H__ */
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