These are needed in some cases on x86 where a compiler barrier is not sufficient - for example, ensuring an rdtsc instruction has executed before subsequent instructions. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I339e2dd6138ccb11b1492e70f7c724976ef3038b Reviewed-on: https://review.gerrithub.io/413145 Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> |
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