We used to ceil the size of the vring structure to the nearest cache line boundary. That's how the original DPDK implementation behaved, but I can't find a reason for this. This patch gets rid of the ceiling. Change-Id: Iaa40fdb79c60252237901f77023ff2f9e580eece Signed-off-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/450549 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> |
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virtio_user | ||
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virtio_pci.c | ||
virtio_user.c | ||
virtio.c |