51606ed402
Initial support for softare AESNI_MB DPDK driver only. Have tested (both aesni and QAT seprately and concurrrently) on underlying NVMe devices with bdevio and a bdevperf script that runs IOs from 512B to 128K each with Q depths from 1 to 512 in powers of 2 for 30 seconds each run. QAT can be included in the code (but not makefile) and marked as experimental until we are ready to test in CI. It works well on 2 systems but is a big PITA to get the hardware setup and configured for use with DPDK (IMHO). Change-Id: If518c3df8e74e00efa18afdf194824c5e69778fc Signed-off-by: Paul Luse <paul.e.luse@intel.com> Reviewed-on: https://review.gerrithub.io/403107 Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*-
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*
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* Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
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* Copyright 2014 6WIND S.A.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTE_MBUF_H_
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#define _RTE_MBUF_H_
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#include "rte_mempool.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* In order to mock some DPDK functions, we place headers here with the name name as the DPDK headers
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* so these definitions wil be picked up. Only what's mocked is included.
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*/
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__extension__
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typedef void *MARKER[0];
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__extension__
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typedef uint8_t MARKER8[0];
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__extension__
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typedef uint64_t MARKER64[0];
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struct rte_mbuf {
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MARKER cacheline0;
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void *buf_addr;
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RTE_STD_C11
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union {
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rte_iova_t buf_iova;
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rte_iova_t buf_physaddr;
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} __rte_aligned(sizeof(rte_iova_t));
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MARKER64 rearm_data;
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uint16_t data_off;
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RTE_STD_C11
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union {
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rte_atomic16_t refcnt_atomic;
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uint16_t refcnt;
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};
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uint16_t nb_segs;
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uint16_t port;
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uint64_t ol_flags;
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MARKER rx_descriptor_fields1;
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RTE_STD_C11
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union {
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uint32_t packet_type;
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struct {
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uint32_t l2_type: 4;
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uint32_t l3_type: 4;
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uint32_t l4_type: 4;
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uint32_t tun_type: 4;
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RTE_STD_C11
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union {
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uint8_t inner_esp_next_proto;
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__extension__
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struct {
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uint8_t inner_l2_type: 4;
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uint8_t inner_l3_type: 4;
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};
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};
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uint32_t inner_l4_type: 4;
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};
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};
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uint32_t pkt_len;
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uint16_t data_len;
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uint16_t vlan_tci;
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union {
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uint32_t rss;
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struct {
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RTE_STD_C11
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union {
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struct {
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uint16_t hash;
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uint16_t id;
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};
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uint32_t lo;
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};
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uint32_t hi;
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} fdir;
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struct {
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uint32_t lo;
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uint32_t hi;
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} sched;
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uint32_t usr;
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} hash;
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uint16_t vlan_tci_outer;
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uint16_t buf_len;
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uint64_t timestamp;
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MARKER cacheline1 __rte_cache_min_aligned;
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RTE_STD_C11
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union {
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void *userdata;
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uint64_t udata64;
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};
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struct rte_mempool *pool;
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struct rte_mbuf *next;
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RTE_STD_C11
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union {
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uint64_t tx_offload;
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__extension__
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struct {
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uint64_t l2_len: 7;
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uint64_t l3_len: 9;
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uint64_t l4_len: 8;
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uint64_t tso_segsz: 16;
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uint64_t outer_l3_len: 9;
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uint64_t outer_l2_len: 7;
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};
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};
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uint16_t priv_size;
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uint16_t timesync;
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uint32_t seqn;
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} __rte_cache_aligned;
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#ifdef __cplusplus
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}
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#endif
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#endif
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