8696cd4288
Allow user to add seed value for guard compuation to DIF context. This will avoid the guard being zero in case of all zero data. NVMe controller doesn't support seed value for guard computation explicitly, and hence if we want to use such a seed value in NVMe controller, we have to format metadata more than 8 byte, and add seed value into the reserved metadata field. But some popular iSCSI/FC HBAs and SAS controllers have supported seed value for guard computation, and so supporting seed value in the SPDK DIF library is very helpful for some use cases. Hence this patch makes the DIF library possible to specify seed value for those use cases. Change-Id: I7e9e87cb441bf263e64605c7820409fdc22dd977 Signed-off-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com> Reviewed-on: https://review.gerrithub.io/c/444334 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com> Reviewed-by: wuzhouhui <wuzhouhui@kingsoft.com>
1444 lines
42 KiB
C
1444 lines
42 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "spdk/stdinc.h"
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#include "spdk_cunit.h"
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#include "util/dif.c"
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#define DATA_PATTERN 0xAB
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#define GUARD_SEED 0xCD
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static int
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ut_data_pattern_generate(struct iovec *iovs, int iovcnt,
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uint32_t block_size, uint32_t md_size, uint32_t num_blocks)
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{
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struct _iov_iter iter;
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uint32_t offset_blocks, offset_in_block, buf_len;
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void *buf;
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if (!_are_iovs_valid(iovs, iovcnt, block_size * num_blocks)) {
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return -1;
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}
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offset_blocks = 0;
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_iov_iter_init(&iter, iovs, iovcnt);
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while (offset_blocks < num_blocks) {
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offset_in_block = 0;
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while (offset_in_block < block_size) {
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_iov_iter_get_buf(&iter, &buf, &buf_len);
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if (offset_in_block < block_size - md_size) {
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buf_len = spdk_min(buf_len,
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block_size - md_size - offset_in_block);
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memset(buf, DATA_PATTERN, buf_len);
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} else {
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buf_len = spdk_min(buf_len, block_size - offset_in_block);
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memset(buf, 0, buf_len);
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}
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_iov_iter_advance(&iter, buf_len);
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offset_in_block += buf_len;
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}
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offset_blocks++;
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}
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return 0;
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}
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static int
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ut_data_pattern_verify(struct iovec *iovs, int iovcnt,
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uint32_t block_size, uint32_t md_size, uint32_t num_blocks)
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{
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struct _iov_iter iter;
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uint32_t offset_blocks, offset_in_block, buf_len, i;
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uint8_t *buf;
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if (!_are_iovs_valid(iovs, iovcnt, block_size * num_blocks)) {
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return -1;
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}
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offset_blocks = 0;
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_iov_iter_init(&iter, iovs, iovcnt);
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while (offset_blocks < num_blocks) {
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offset_in_block = 0;
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while (offset_in_block < block_size) {
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_iov_iter_get_buf(&iter, (void *)&buf, &buf_len);
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if (offset_in_block < block_size - md_size) {
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buf_len = spdk_min(buf_len,
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block_size - md_size - offset_in_block);
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for (i = 0; i < buf_len; i++) {
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if (buf[i] != DATA_PATTERN) {
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return -1;
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}
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}
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} else {
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buf_len = spdk_min(buf_len, block_size - offset_in_block);
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}
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_iov_iter_advance(&iter, buf_len);
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offset_in_block += buf_len;
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}
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offset_blocks++;
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}
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return 0;
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}
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static void
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_iov_alloc_buf(struct iovec *iov, uint32_t len)
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{
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iov->iov_base = calloc(1, len);
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iov->iov_len = len;
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SPDK_CU_ASSERT_FATAL(iov->iov_base != NULL);
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}
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static void
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_iov_free_buf(struct iovec *iov)
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{
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free(iov->iov_base);
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}
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static void
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_dif_generate_and_verify(struct iovec *iov,
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uint32_t block_size, uint32_t md_size, bool dif_loc,
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enum spdk_dif_type dif_type, uint32_t dif_flags,
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uint32_t ref_tag, uint32_t e_ref_tag,
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uint16_t app_tag, uint16_t apptag_mask, uint16_t e_app_tag,
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bool expect_pass)
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{
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struct spdk_dif_ctx ctx = {};
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uint32_t guard_interval;
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uint16_t guard = 0;
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int rc;
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rc = ut_data_pattern_generate(iov, 1, block_size, md_size, 1);
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CU_ASSERT(rc == 0);
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guard_interval = _get_guard_interval(block_size, md_size, dif_loc, true);
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ctx.dif_type = dif_type;
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ctx.dif_flags = dif_flags;
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ctx.init_ref_tag = ref_tag;
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ctx.app_tag = app_tag;
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if (dif_flags & SPDK_DIF_FLAGS_GUARD_CHECK) {
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guard = spdk_crc16_t10dif(0, iov->iov_base, guard_interval);
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}
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_dif_generate(iov->iov_base + guard_interval, guard, 0, &ctx);
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ctx.init_ref_tag = e_ref_tag;
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ctx.apptag_mask = apptag_mask;
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ctx.app_tag = e_app_tag;
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rc = _dif_verify(iov->iov_base + guard_interval, guard, 0, &ctx, NULL);
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CU_ASSERT((expect_pass && rc == 0) || (!expect_pass && rc != 0));
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rc = ut_data_pattern_verify(iov, 1, block_size, md_size, 1);
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CU_ASSERT(rc == 0);
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}
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static void
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dif_generate_and_verify_test(void)
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{
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struct iovec iov;
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uint32_t dif_flags;
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dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
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SPDK_DIF_FLAGS_REFTAG_CHECK;
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_iov_alloc_buf(&iov, 4096 + 128);
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/* Positive cases */
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/* The case that DIF is contained in the first 8 bytes of metadata. */
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, true,
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SPDK_DIF_TYPE1, dif_flags,
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22, 22,
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0x22, 0xFFFF, 0x22,
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true);
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/* The case that DIF is contained in the last 8 bytes of metadata. */
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, false,
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SPDK_DIF_TYPE1, dif_flags,
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22, 22,
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0x22, 0xFFFF, 0x22,
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true);
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/* Negative cases */
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/* Reference tag doesn't match. */
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, false,
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SPDK_DIF_TYPE1, dif_flags,
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22, 23,
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0x22, 0xFFFF, 0x22,
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false);
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/* Application tag doesn't match. */
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, false,
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SPDK_DIF_TYPE1, dif_flags,
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22, 22,
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0x22, 0xFFFF, 0x23,
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false);
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_iov_free_buf(&iov);
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}
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static void
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dif_disable_check_test(void)
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{
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struct iovec iov;
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uint32_t dif_flags;
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dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
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SPDK_DIF_FLAGS_REFTAG_CHECK;
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_iov_alloc_buf(&iov, 4096 + 128);
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/* The case that DIF check is disabled when the Application Tag is 0xFFFF for
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* Type 1. DIF check is disabled and pass is expected.
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*/
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, false,
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SPDK_DIF_TYPE1, dif_flags,
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22, 22,
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0xFFFF, 0xFFFF, 0x22,
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true);
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/* The case that DIF check is not disabled when the Application Tag is 0xFFFF but
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* the Reference Tag is not 0xFFFFFFFF for Type 3. DIF check is not disabled and
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* fail is expected.
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*/
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, false,
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SPDK_DIF_TYPE3, dif_flags,
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22, 22,
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0xFFFF, 0xFFFF, 0x22,
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false);
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/* The case that DIF check is disabled when the Application Tag is 0xFFFF and
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* the Reference Tag is 0xFFFFFFFF for Type 3. DIF check is disabled and
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* pass is expected.
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*/
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_dif_generate_and_verify(&iov,
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4096 + 128, 128, false,
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SPDK_DIF_TYPE3, dif_flags,
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0xFFFFFFFF, 22,
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0xFFFF, 0xFFFF, 0x22,
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true);
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_iov_free_buf(&iov);
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}
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static void
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dif_sec_512_md_0_error_test(void)
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{
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struct spdk_dif_ctx ctx = {};
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int rc;
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/* Metadata size is 0. */
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rc = spdk_dif_ctx_init(&ctx, 512, 0, true, false, SPDK_DIF_TYPE1, 0, 0, 0, 0, 0);
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CU_ASSERT(rc != 0);
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}
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static void
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dif_guard_seed_test(void)
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{
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struct iovec iov;
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struct spdk_dif_ctx ctx = {};
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struct spdk_dif_error err_blk = {};
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struct spdk_dif *dif;
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uint16_t guard;
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int rc;
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_iov_alloc_buf(&iov, 512 + 8);
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memset(iov.iov_base, 0, 512 + 8);
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dif = (struct spdk_dif *)(iov.iov_base + 512);
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rc = spdk_dif_ctx_init(&ctx, 512 + 8, 8, true, false, SPDK_DIF_TYPE1,
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SPDK_DIF_FLAGS_GUARD_CHECK, 0, 0, 0, 0);
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CU_ASSERT(rc == 0);
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rc = spdk_dif_generate(&iov, 1, 1, &ctx);
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CU_ASSERT(rc == 0);
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/* Guard should be zero if the block is all zero and seed is not added. */
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guard = from_be16(&dif->guard);
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CU_ASSERT(guard == 0);
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rc = spdk_dif_verify(&iov, 1, 1, &ctx, &err_blk);
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CU_ASSERT(rc == 0);
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rc = spdk_dif_ctx_init(&ctx, 512 + 8, 8, true, false, SPDK_DIF_TYPE1,
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SPDK_DIF_FLAGS_GUARD_CHECK, 0, 0, 0, GUARD_SEED);
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CU_ASSERT(rc == 0);
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rc = spdk_dif_generate(&iov, 1, 1, &ctx);
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CU_ASSERT(rc == 0);
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/* Guard should not be zero if the block is all zero but seed is added. */
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guard = from_be16(&dif->guard);
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CU_ASSERT(guard != 0);
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rc = spdk_dif_verify(&iov, 1, 1, &ctx, &err_blk);
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CU_ASSERT(rc == 0);
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_iov_free_buf(&iov);
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}
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static void
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dif_generate_and_verify(struct iovec *iovs, int iovcnt,
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uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
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bool dif_loc, enum spdk_dif_type dif_type, uint32_t dif_flags,
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uint32_t init_ref_tag, uint16_t apptag_mask, uint16_t app_tag)
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{
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struct spdk_dif_ctx ctx = {};
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int rc;
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rc = ut_data_pattern_generate(iovs, iovcnt, block_size, md_size, num_blocks);
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CU_ASSERT(rc == 0);
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rc = spdk_dif_ctx_init(&ctx, block_size, md_size, true, dif_loc, dif_type, dif_flags,
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init_ref_tag, apptag_mask, app_tag, GUARD_SEED);
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CU_ASSERT(rc == 0);
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rc = spdk_dif_generate(iovs, iovcnt, num_blocks, &ctx);
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CU_ASSERT(rc == 0);
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rc = spdk_dif_verify(iovs, iovcnt, num_blocks, &ctx, NULL);
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CU_ASSERT(rc == 0);
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rc = ut_data_pattern_verify(iovs, iovcnt, block_size, md_size, num_blocks);
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CU_ASSERT(rc == 0);
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}
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static void
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dif_disable_sec_512_md_8_single_iov_test(void)
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{
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struct iovec iov;
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_iov_alloc_buf(&iov, (512 + 8) * 4);
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dif_generate_and_verify(&iov, 1, 512 + 8, 8, 1, false, SPDK_DIF_DISABLE, 0, 0, 0, 0);
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_iov_free_buf(&iov);
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}
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static void
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dif_sec_512_md_8_prchk_0_single_iov_test(void)
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{
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struct iovec iov;
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_iov_alloc_buf(&iov, (512 + 8) * 4);
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dif_generate_and_verify(&iov, 1, 512 + 8, 8, 1, false, SPDK_DIF_TYPE1, 0, 0, 0, 0);
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_iov_free_buf(&iov);
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}
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static void
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dif_sec_512_md_8_prchk_0_1_2_4_multi_iovs_test(void)
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{
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struct iovec iovs[4];
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int i, num_blocks;
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num_blocks = 0;
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for (i = 0; i < 4; i++) {
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_iov_alloc_buf(&iovs[i], (512 + 8) * (i + 1));
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num_blocks += i + 1;
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}
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dif_generate_and_verify(iovs, 4, 512 + 8, 8, num_blocks, false, SPDK_DIF_TYPE1,
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0, 22, 0xFFFF, 0x22);
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dif_generate_and_verify(iovs, 4, 512 + 8, 8, num_blocks, false, SPDK_DIF_TYPE1,
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SPDK_DIF_FLAGS_GUARD_CHECK, 22, 0xFFFF, 0x22);
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dif_generate_and_verify(iovs, 4, 512 + 8, 8, num_blocks, false, SPDK_DIF_TYPE1,
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SPDK_DIF_FLAGS_APPTAG_CHECK, 22, 0xFFFF, 0x22);
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dif_generate_and_verify(iovs, 4, 512 + 8, 8, num_blocks, false, SPDK_DIF_TYPE1,
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SPDK_DIF_FLAGS_REFTAG_CHECK, 22, 0xFFFF, 0x22);
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for (i = 0; i < 4; i++) {
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_iov_free_buf(&iovs[i]);
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}
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}
|
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|
|
static void
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dif_sec_4096_md_128_prchk_7_multi_iovs_test(void)
|
|
{
|
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struct iovec iovs[4];
|
|
int i, num_blocks;
|
|
uint32_t dif_flags;
|
|
|
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dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
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SPDK_DIF_FLAGS_REFTAG_CHECK;
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num_blocks = 0;
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|
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for (i = 0; i < 4; i++) {
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_iov_alloc_buf(&iovs[i], (4096 + 128) * (i + 1));
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num_blocks += i + 1;
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}
|
|
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dif_generate_and_verify(iovs, 4, 4096 + 128, 128, num_blocks, false, SPDK_DIF_TYPE1,
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dif_flags, 22, 0xFFFF, 0x22);
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dif_generate_and_verify(iovs, 4, 4096 + 128, 128, num_blocks, true, SPDK_DIF_TYPE1,
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dif_flags, 22, 0xFFFF, 0x22);
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|
|
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for (i = 0; i < 4; i++) {
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_iov_free_buf(&iovs[i]);
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|
}
|
|
}
|
|
|
|
static void
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_data_and_md_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
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|
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_iov_alloc_buf(&iovs[0], 512);
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_iov_alloc_buf(&iovs[1], 8);
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dif_generate_and_verify(iovs, 2, 512 + 8, 8, 1, false, SPDK_DIF_TYPE1,
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dif_flags, 22, 0xFFFF, 0x22);
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|
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_iov_free_buf(&iovs[0]);
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_iov_free_buf(&iovs[1]);
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}
|
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|
|
static void
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_data_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
_iov_alloc_buf(&iovs[0], 256);
|
|
_iov_alloc_buf(&iovs[1], 264);
|
|
|
|
dif_generate_and_verify(iovs, 2, 512 + 8, 8, 1, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_guard_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
_iov_alloc_buf(&iovs[0], 513);
|
|
_iov_alloc_buf(&iovs[1], 7);
|
|
|
|
dif_generate_and_verify(iovs, 2, 512 + 8, 8, 1, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_apptag_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
_iov_alloc_buf(&iovs[0], 515);
|
|
_iov_alloc_buf(&iovs[1], 5);
|
|
|
|
dif_generate_and_verify(iovs, 2, 512 + 8, 8, 1, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_reftag_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
_iov_alloc_buf(&iovs[0], 518);
|
|
_iov_alloc_buf(&iovs[1], 2);
|
|
|
|
dif_generate_and_verify(iovs, 2, 512 + 8, 8, 1, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_complex_splits_test(void)
|
|
{
|
|
struct iovec iovs[9];
|
|
uint32_t dif_flags;
|
|
int i;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
/* data[0][255:0] */
|
|
_iov_alloc_buf(&iovs[0], 256);
|
|
|
|
/* data[0][511:256], guard[0][0] */
|
|
_iov_alloc_buf(&iovs[1], 256 + 1);
|
|
|
|
/* guard[0][1], apptag[0][0] */
|
|
_iov_alloc_buf(&iovs[2], 1 + 1);
|
|
|
|
/* apptag[0][1], reftag[0][0] */
|
|
_iov_alloc_buf(&iovs[3], 1 + 1);
|
|
|
|
/* reftag[0][3:1], data[1][255:0] */
|
|
_iov_alloc_buf(&iovs[4], 3 + 256);
|
|
|
|
/* data[1][511:256], guard[1][0] */
|
|
_iov_alloc_buf(&iovs[5], 256 + 1);
|
|
|
|
/* guard[1][1], apptag[1][0] */
|
|
_iov_alloc_buf(&iovs[6], 1 + 1);
|
|
|
|
/* apptag[1][1], reftag[1][0] */
|
|
_iov_alloc_buf(&iovs[7], 1 + 1);
|
|
|
|
/* reftag[1][3:1] */
|
|
_iov_alloc_buf(&iovs[8], 3);
|
|
|
|
dif_generate_and_verify(iovs, 9, 512 + 8, 8, 2, false, SPDK_DIF_TYPE1, dif_flags,
|
|
22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 9; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_prchk_7_multi_iovs_complex_splits_test(void)
|
|
{
|
|
struct iovec iovs[11];
|
|
uint32_t dif_flags;
|
|
int i;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
/* data[0][1000:0] */
|
|
_iov_alloc_buf(&iovs[0], 1000);
|
|
|
|
/* data[0][3095:1000], guard[0][0] */
|
|
_iov_alloc_buf(&iovs[1], 3096 + 1);
|
|
|
|
/* guard[0][1], apptag[0][0] */
|
|
_iov_alloc_buf(&iovs[2], 1 + 1);
|
|
|
|
/* apptag[0][1], reftag[0][0] */
|
|
_iov_alloc_buf(&iovs[3], 1 + 1);
|
|
|
|
/* reftag[0][3:1], ignore[0][59:0] */
|
|
_iov_alloc_buf(&iovs[4], 3 + 60);
|
|
|
|
/* ignore[119:60], data[1][3050:0] */
|
|
_iov_alloc_buf(&iovs[5], 60 + 3051);
|
|
|
|
/* data[1][4095:3050], guard[1][0] */
|
|
_iov_alloc_buf(&iovs[6], 1045 + 1);
|
|
|
|
/* guard[1][1], apptag[1][0] */
|
|
_iov_alloc_buf(&iovs[7], 1 + 1);
|
|
|
|
/* apptag[1][1], reftag[1][0] */
|
|
_iov_alloc_buf(&iovs[8], 1 + 1);
|
|
|
|
/* reftag[1][3:1], ignore[1][9:0] */
|
|
_iov_alloc_buf(&iovs[9], 3 + 10);
|
|
|
|
/* ignore[1][127:9] */
|
|
_iov_alloc_buf(&iovs[10], 118);
|
|
|
|
dif_generate_and_verify(iovs, 11, 4096 + 128, 128, 2, false, SPDK_DIF_TYPE1, dif_flags,
|
|
22, 0xFFFF, 0x22);
|
|
dif_generate_and_verify(iovs, 11, 4096 + 128, 128, 2, true, SPDK_DIF_TYPE1, dif_flags,
|
|
22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 11; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
}
|
|
|
|
static void
|
|
_dif_inject_error_and_verify(struct iovec *iovs, int iovcnt,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
uint32_t inject_flags, bool dif_loc)
|
|
{
|
|
struct spdk_dif_ctx ctx = {};
|
|
struct spdk_dif_error err_blk = {};
|
|
uint32_t inject_offset = 0, dif_flags;
|
|
int rc;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
rc = ut_data_pattern_generate(iovs, iovcnt, block_size, md_size, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_ctx_init(&ctx, block_size, md_size, true, dif_loc,
|
|
SPDK_DIF_TYPE1, dif_flags, 88, 0xFFFF, 0x88, GUARD_SEED);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_generate(iovs, iovcnt, num_blocks, &ctx);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_inject_error(iovs, iovcnt, num_blocks, &ctx, inject_flags, &inject_offset);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_verify(iovs, iovcnt, num_blocks, &ctx, &err_blk);
|
|
CU_ASSERT(rc != 0);
|
|
if (inject_flags == SPDK_DIF_DATA_ERROR) {
|
|
CU_ASSERT(SPDK_DIF_GUARD_ERROR == err_blk.err_type);
|
|
} else {
|
|
CU_ASSERT(inject_flags == err_blk.err_type);
|
|
}
|
|
CU_ASSERT(inject_offset == err_blk.err_offset);
|
|
|
|
rc = ut_data_pattern_verify(iovs, iovcnt, block_size, md_size, num_blocks);
|
|
CU_ASSERT((rc == 0 && (inject_flags != SPDK_DIF_DATA_ERROR)) ||
|
|
(rc != 0 && (inject_flags == SPDK_DIF_DATA_ERROR)));
|
|
}
|
|
|
|
static void
|
|
dif_inject_error_and_verify(struct iovec *iovs, int iovcnt,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
uint32_t inject_flags)
|
|
{
|
|
/* The case that DIF is contained in the first 8 bytes of metadata. */
|
|
_dif_inject_error_and_verify(iovs, iovcnt, block_size, md_size, num_blocks,
|
|
inject_flags, true);
|
|
|
|
/* The case that DIF is contained in the last 8 bytes of metadata. */
|
|
_dif_inject_error_and_verify(iovs, iovcnt, block_size, md_size, num_blocks,
|
|
inject_flags, false);
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test(void)
|
|
{
|
|
struct iovec iovs[4];
|
|
int i, num_blocks;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], (4096 + 128) * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
|
|
dif_inject_error_and_verify(iovs, 4, 4096 + 128, 128, num_blocks, SPDK_DIF_GUARD_ERROR);
|
|
dif_inject_error_and_verify(iovs, 4, 4096 + 128, 128, num_blocks, SPDK_DIF_APPTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 4, 4096 + 128, 128, num_blocks, SPDK_DIF_REFTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 4, 4096 + 128, 128, num_blocks, SPDK_DIF_DATA_ERROR);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_data_and_md_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
|
|
_iov_alloc_buf(&iovs[0], 4096);
|
|
_iov_alloc_buf(&iovs[1], 128);
|
|
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_GUARD_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_APPTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_REFTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_DATA_ERROR);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_data_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
|
|
_iov_alloc_buf(&iovs[0], 2048);
|
|
_iov_alloc_buf(&iovs[1], 2048 + 128);
|
|
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_GUARD_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_APPTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_REFTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_DATA_ERROR);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_guard_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
|
|
_iov_alloc_buf(&iovs[0], 4096 + 1);
|
|
_iov_alloc_buf(&iovs[1], 127);
|
|
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_GUARD_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_APPTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_REFTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_DATA_ERROR);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_apptag_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
|
|
_iov_alloc_buf(&iovs[0], 4096 + 3);
|
|
_iov_alloc_buf(&iovs[1], 125);
|
|
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_GUARD_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_APPTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_REFTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_DATA_ERROR);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_reftag_test(void)
|
|
{
|
|
struct iovec iovs[2];
|
|
|
|
_iov_alloc_buf(&iovs[0], 4096 + 6);
|
|
_iov_alloc_buf(&iovs[1], 122);
|
|
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_GUARD_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_APPTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_REFTAG_ERROR);
|
|
dif_inject_error_and_verify(iovs, 2, 4096 + 128, 128, 1, SPDK_DIF_DATA_ERROR);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
}
|
|
|
|
static void
|
|
dif_copy_gen_and_verify(struct iovec *iovs, int iovcnt, struct iovec *bounce_iov,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
bool dif_loc, enum spdk_dif_type dif_type, uint32_t dif_flags,
|
|
uint32_t init_ref_tag, uint16_t apptag_mask, uint16_t app_tag)
|
|
{
|
|
struct spdk_dif_ctx ctx = {};
|
|
int rc;
|
|
|
|
rc = ut_data_pattern_generate(iovs, iovcnt, block_size - md_size, 0, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_ctx_init(&ctx, block_size, md_size, true, dif_loc, dif_type, dif_flags,
|
|
init_ref_tag, apptag_mask, app_tag, GUARD_SEED);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_generate_copy(iovs, iovcnt, bounce_iov, num_blocks, &ctx);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_verify_copy(iovs, iovcnt, bounce_iov, num_blocks, &ctx, NULL);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = ut_data_pattern_verify(iovs, iovcnt, block_size - md_size, 0, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_512_md_8_prchk_0_single_iov(void)
|
|
{
|
|
struct iovec iov, bounce_iov;
|
|
|
|
_iov_alloc_buf(&iov, 512 * 4);
|
|
_iov_alloc_buf(&bounce_iov, (512 + 8) * 4);
|
|
|
|
dif_copy_gen_and_verify(&iov, 1, &bounce_iov, 512 + 8, 8, 4,
|
|
false, SPDK_DIF_TYPE1, 0, 0, 0, 0);
|
|
dif_copy_gen_and_verify(&iov, 1, &bounce_iov, 512 + 8, 8, 4,
|
|
true, SPDK_DIF_TYPE1, 0, 0, 0, 0);
|
|
|
|
_iov_free_buf(&iov);
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_512_md_8_prchk_0_1_2_4_multi_iovs(void)
|
|
{
|
|
struct iovec iovs[4], bounce_iov;
|
|
int i, num_blocks;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], 512 * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
|
|
_iov_alloc_buf(&bounce_iov, (512 + 8) * num_blocks);
|
|
|
|
dif_copy_gen_and_verify(iovs, 4, &bounce_iov, 512 + 8, 8, num_blocks,
|
|
false, SPDK_DIF_TYPE1, 0, 22, 0xFFFF, 0x22);
|
|
|
|
dif_copy_gen_and_verify(iovs, 4, &bounce_iov, 512 + 8, 8, num_blocks,
|
|
false, SPDK_DIF_TYPE1, SPDK_DIF_FLAGS_GUARD_CHECK, 22, 0xFFFF, 0x22);
|
|
|
|
dif_copy_gen_and_verify(iovs, 4, &bounce_iov, 512 + 8, 8, num_blocks,
|
|
false, SPDK_DIF_TYPE1, SPDK_DIF_FLAGS_APPTAG_CHECK, 22, 0xFFFF, 0x22);
|
|
|
|
dif_copy_gen_and_verify(iovs, 4, &bounce_iov, 512 + 8, 8, num_blocks,
|
|
false, SPDK_DIF_TYPE1, SPDK_DIF_FLAGS_REFTAG_CHECK, 22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_4096_md_128_prchk_7_multi_iovs(void)
|
|
{
|
|
struct iovec iovs[4], bounce_iov;
|
|
uint32_t dif_flags;
|
|
int i, num_blocks;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], 4096 * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
|
|
_iov_alloc_buf(&bounce_iov, (4096 + 128) * num_blocks);
|
|
|
|
dif_copy_gen_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128, num_blocks,
|
|
false, SPDK_DIF_TYPE1, dif_flags, 22, 0xFFFF, 0x22);
|
|
dif_copy_gen_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128, num_blocks,
|
|
true, SPDK_DIF_TYPE1, dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_512_md_8_prchk_7_multi_iovs_split_data(void)
|
|
{
|
|
struct iovec iovs[2], bounce_iov;
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
_iov_alloc_buf(&iovs[0], 256);
|
|
_iov_alloc_buf(&iovs[1], 256);
|
|
|
|
_iov_alloc_buf(&bounce_iov, 512 + 8);
|
|
|
|
dif_copy_gen_and_verify(iovs, 2, &bounce_iov, 512 + 8, 8, 1,
|
|
false, SPDK_DIF_TYPE1, dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_512_md_8_prchk_7_multi_iovs_complex_splits(void)
|
|
{
|
|
struct iovec iovs[6], bounce_iov;
|
|
uint32_t dif_flags;
|
|
int i;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
/* data[0][255:0] */
|
|
_iov_alloc_buf(&iovs[0], 256);
|
|
|
|
/* data[0][511:256], data[1][255:0] */
|
|
_iov_alloc_buf(&iovs[1], 256 + 256);
|
|
|
|
/* data[1][382:256] */
|
|
_iov_alloc_buf(&iovs[2], 128);
|
|
|
|
/* data[1][383] */
|
|
_iov_alloc_buf(&iovs[3], 1);
|
|
|
|
/* data[1][510:384] */
|
|
_iov_alloc_buf(&iovs[4], 126);
|
|
|
|
/* data[1][511], data[2][511:0], data[3][511:0] */
|
|
_iov_alloc_buf(&iovs[5], 1 + 512 * 2);
|
|
|
|
_iov_alloc_buf(&bounce_iov, (512 + 8) * 4);
|
|
|
|
dif_copy_gen_and_verify(iovs, 6, &bounce_iov, 512 + 8, 8, 4,
|
|
true, SPDK_DIF_TYPE1, dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
_dif_copy_inject_error_and_verify(struct iovec *iovs, int iovcnt, struct iovec *bounce_iov,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
uint32_t inject_flags, bool dif_loc)
|
|
{
|
|
struct spdk_dif_ctx ctx = {};
|
|
struct spdk_dif_error err_blk = {};
|
|
uint32_t inject_offset = 0, dif_flags;
|
|
int rc;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
rc = ut_data_pattern_generate(iovs, iovcnt, block_size - md_size, 0, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_ctx_init(&ctx, block_size, md_size, true, dif_loc, SPDK_DIF_TYPE1, dif_flags,
|
|
88, 0xFFFF, 0x88, GUARD_SEED);
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
rc = spdk_dif_generate_copy(iovs, iovcnt, bounce_iov, num_blocks, &ctx);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_inject_error(bounce_iov, 1, num_blocks, &ctx, inject_flags, &inject_offset);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_verify_copy(iovs, iovcnt, bounce_iov, num_blocks, &ctx, &err_blk);
|
|
CU_ASSERT(rc != 0);
|
|
if (inject_flags == SPDK_DIF_DATA_ERROR) {
|
|
CU_ASSERT(SPDK_DIF_GUARD_ERROR == err_blk.err_type);
|
|
} else {
|
|
CU_ASSERT(inject_flags == err_blk.err_type);
|
|
}
|
|
CU_ASSERT(inject_offset == err_blk.err_offset);
|
|
}
|
|
|
|
static void
|
|
dif_copy_inject_error_and_verify(struct iovec *iovs, int iovcnt, struct iovec *bounce_iov,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
uint32_t inject_flags)
|
|
{
|
|
/* The case that DIF is contained in the first 8 bytes of metadata. */
|
|
_dif_copy_inject_error_and_verify(iovs, iovcnt, bounce_iov,
|
|
block_size, md_size, num_blocks,
|
|
inject_flags, true);
|
|
|
|
/* The case that DIF is contained in the last 8 bytes of metadata. */
|
|
_dif_copy_inject_error_and_verify(iovs, iovcnt, bounce_iov,
|
|
block_size, md_size, num_blocks,
|
|
inject_flags, false);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test(void)
|
|
{
|
|
struct iovec iovs[4], bounce_iov;
|
|
int i, num_blocks;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], 4096 * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
|
|
_iov_alloc_buf(&bounce_iov, (4096 + 128) * num_blocks);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
num_blocks, SPDK_DIF_GUARD_ERROR);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
num_blocks, SPDK_DIF_APPTAG_ERROR);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
num_blocks, SPDK_DIF_REFTAG_ERROR);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
num_blocks, SPDK_DIF_DATA_ERROR);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
dif_copy_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_test(void)
|
|
{
|
|
struct iovec iovs[4], bounce_iov;
|
|
int i;
|
|
|
|
_iov_alloc_buf(&iovs[0], 2048);
|
|
_iov_alloc_buf(&iovs[1], 2048);
|
|
_iov_alloc_buf(&iovs[2], 1);
|
|
_iov_alloc_buf(&iovs[3], 4095);
|
|
|
|
_iov_alloc_buf(&bounce_iov, (4096 + 128) * 2);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
2, SPDK_DIF_GUARD_ERROR);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
2, SPDK_DIF_APPTAG_ERROR);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
2, SPDK_DIF_REFTAG_ERROR);
|
|
|
|
dif_copy_inject_error_and_verify(iovs, 4, &bounce_iov, 4096 + 128, 128,
|
|
2, SPDK_DIF_DATA_ERROR);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&bounce_iov);
|
|
}
|
|
|
|
static void
|
|
dix_sec_512_md_0_error(void)
|
|
{
|
|
struct spdk_dif_ctx ctx;
|
|
int rc;
|
|
|
|
rc = spdk_dif_ctx_init(&ctx, 512, 0, false, false, SPDK_DIF_TYPE1, 0, 0, 0, 0, 0);
|
|
CU_ASSERT(rc != 0);
|
|
}
|
|
|
|
static void
|
|
dix_generate_and_verify(struct iovec *iovs, int iovcnt, struct iovec *md_iov,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
bool dif_loc, enum spdk_dif_type dif_type, uint32_t dif_flags,
|
|
uint32_t init_ref_tag, uint16_t apptag_mask, uint16_t app_tag)
|
|
{
|
|
struct spdk_dif_ctx ctx;
|
|
int rc;
|
|
|
|
rc = ut_data_pattern_generate(iovs, iovcnt, block_size, 0, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_ctx_init(&ctx, block_size, md_size, false, dif_loc, dif_type, dif_flags,
|
|
init_ref_tag, apptag_mask, app_tag, GUARD_SEED);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dix_generate(iovs, iovcnt, md_iov, num_blocks, &ctx);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dix_verify(iovs, iovcnt, md_iov, num_blocks, &ctx, NULL);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = ut_data_pattern_verify(iovs, iovcnt, block_size, 0, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
}
|
|
|
|
static void
|
|
dix_sec_512_md_8_prchk_0_single_iov(void)
|
|
{
|
|
struct iovec iov, md_iov;
|
|
|
|
_iov_alloc_buf(&iov, 512 * 4);
|
|
_iov_alloc_buf(&md_iov, 8 * 4);
|
|
|
|
dix_generate_and_verify(&iov, 1, &md_iov, 512, 8, 4, false, SPDK_DIF_TYPE1, 0, 0, 0, 0);
|
|
dix_generate_and_verify(&iov, 1, &md_iov, 512, 8, 4, true, SPDK_DIF_TYPE1, 0, 0, 0, 0);
|
|
|
|
_iov_free_buf(&iov);
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
static void
|
|
dix_sec_512_md_8_prchk_0_1_2_4_multi_iovs(void)
|
|
{
|
|
struct iovec iovs[4], md_iov;
|
|
int i, num_blocks;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], 512 * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
_iov_alloc_buf(&md_iov, 8 * num_blocks);
|
|
|
|
dix_generate_and_verify(iovs, 4, &md_iov, 512, 8, num_blocks, false, SPDK_DIF_TYPE1,
|
|
0, 22, 0xFFFF, 0x22);
|
|
|
|
dix_generate_and_verify(iovs, 4, &md_iov, 512, 8, num_blocks, false, SPDK_DIF_TYPE1,
|
|
SPDK_DIF_FLAGS_GUARD_CHECK, 22, 0xFFFF, 0x22);
|
|
|
|
dix_generate_and_verify(iovs, 4, &md_iov, 512, 8, num_blocks, false, SPDK_DIF_TYPE1,
|
|
SPDK_DIF_FLAGS_APPTAG_CHECK, 22, 0xFFFF, 0x22);
|
|
|
|
dix_generate_and_verify(iovs, 4, &md_iov, 512, 8, num_blocks, false, SPDK_DIF_TYPE1,
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK, 22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
static void
|
|
dix_sec_4096_md_128_prchk_7_multi_iovs(void)
|
|
{
|
|
struct iovec iovs[4], md_iov;
|
|
uint32_t dif_flags;
|
|
int i, num_blocks;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], 4096 * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
_iov_alloc_buf(&md_iov, 128 * num_blocks);
|
|
|
|
dix_generate_and_verify(iovs, 4, &md_iov, 4096, 128, num_blocks, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
dix_generate_and_verify(iovs, 4, &md_iov, 4096, 128, num_blocks, true, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
static void
|
|
dix_sec_512_md_8_prchk_7_multi_iovs_split_data(void)
|
|
{
|
|
struct iovec iovs[2], md_iov;
|
|
uint32_t dif_flags;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
_iov_alloc_buf(&iovs[0], 256);
|
|
_iov_alloc_buf(&iovs[1], 256);
|
|
_iov_alloc_buf(&md_iov, 8);
|
|
|
|
dix_generate_and_verify(iovs, 2, &md_iov, 512, 8, 1, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
_iov_free_buf(&iovs[0]);
|
|
_iov_free_buf(&iovs[1]);
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
static void
|
|
dix_sec_512_md_8_prchk_7_multi_iovs_complex_splits(void)
|
|
{
|
|
struct iovec iovs[6], md_iov;
|
|
uint32_t dif_flags;
|
|
int i;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
/* data[0][255:0] */
|
|
_iov_alloc_buf(&iovs[0], 256);
|
|
|
|
/* data[0][511:256], data[1][255:0] */
|
|
_iov_alloc_buf(&iovs[1], 256 + 256);
|
|
|
|
/* data[1][382:256] */
|
|
_iov_alloc_buf(&iovs[2], 128);
|
|
|
|
/* data[1][383] */
|
|
_iov_alloc_buf(&iovs[3], 1);
|
|
|
|
/* data[1][510:384] */
|
|
_iov_alloc_buf(&iovs[4], 126);
|
|
|
|
/* data[1][511], data[2][511:0], data[3][511:0] */
|
|
_iov_alloc_buf(&iovs[5], 1 + 512 * 2);
|
|
|
|
_iov_alloc_buf(&md_iov, 8 * 4);
|
|
|
|
dix_generate_and_verify(iovs, 6, &md_iov, 512, 8, 4, false, SPDK_DIF_TYPE1,
|
|
dif_flags, 22, 0xFFFF, 0x22);
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
static void
|
|
_dix_inject_error_and_verify(struct iovec *iovs, int iovcnt, struct iovec *md_iov,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
uint32_t inject_flags, bool dif_loc)
|
|
{
|
|
struct spdk_dif_ctx ctx = {};
|
|
struct spdk_dif_error err_blk = {};
|
|
uint32_t inject_offset = 0, dif_flags;
|
|
int rc;
|
|
|
|
dif_flags = SPDK_DIF_FLAGS_GUARD_CHECK | SPDK_DIF_FLAGS_APPTAG_CHECK |
|
|
SPDK_DIF_FLAGS_REFTAG_CHECK;
|
|
|
|
rc = ut_data_pattern_generate(iovs, iovcnt, block_size, 0, num_blocks);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dif_ctx_init(&ctx, block_size, md_size, false, dif_loc, SPDK_DIF_TYPE1, dif_flags,
|
|
88, 0xFFFF, 0x88, GUARD_SEED);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dix_generate(iovs, iovcnt, md_iov, num_blocks, &ctx);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dix_inject_error(iovs, iovcnt, md_iov, num_blocks, &ctx, inject_flags, &inject_offset);
|
|
CU_ASSERT(rc == 0);
|
|
|
|
rc = spdk_dix_verify(iovs, iovcnt, md_iov, num_blocks, &ctx, &err_blk);
|
|
CU_ASSERT(rc != 0);
|
|
|
|
if (inject_flags == SPDK_DIF_DATA_ERROR) {
|
|
CU_ASSERT(SPDK_DIF_GUARD_ERROR == err_blk.err_type);
|
|
} else {
|
|
CU_ASSERT(inject_flags == err_blk.err_type);
|
|
}
|
|
CU_ASSERT(inject_offset == err_blk.err_offset);
|
|
}
|
|
|
|
static void
|
|
dix_inject_error_and_verify(struct iovec *iovs, int iovcnt, struct iovec *md_iov,
|
|
uint32_t block_size, uint32_t md_size, uint32_t num_blocks,
|
|
uint32_t inject_flags)
|
|
{
|
|
/* The case that DIF is contained in the first 8 bytes of metadata. */
|
|
_dix_inject_error_and_verify(iovs, iovcnt, md_iov, block_size, md_size, num_blocks,
|
|
inject_flags, true);
|
|
|
|
/* The case that DIF is contained in the last 8 bytes of metadata. */
|
|
_dix_inject_error_and_verify(iovs, iovcnt, md_iov, block_size, md_size, num_blocks,
|
|
inject_flags, false);
|
|
}
|
|
|
|
static void
|
|
dix_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test(void)
|
|
{
|
|
struct iovec iovs[4], md_iov;
|
|
int i, num_blocks;
|
|
|
|
num_blocks = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_alloc_buf(&iovs[i], 4096 * (i + 1));
|
|
num_blocks += i + 1;
|
|
}
|
|
|
|
_iov_alloc_buf(&md_iov, 128 * num_blocks);
|
|
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, num_blocks, SPDK_DIF_GUARD_ERROR);
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, num_blocks, SPDK_DIF_APPTAG_ERROR);
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, num_blocks, SPDK_DIF_REFTAG_ERROR);
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, num_blocks, SPDK_DIF_DATA_ERROR);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
static void
|
|
dix_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_test(void)
|
|
{
|
|
struct iovec iovs[4], md_iov;
|
|
int i;
|
|
|
|
_iov_alloc_buf(&iovs[0], 2048);
|
|
_iov_alloc_buf(&iovs[1], 2048);
|
|
_iov_alloc_buf(&iovs[2], 1);
|
|
_iov_alloc_buf(&iovs[3], 4095);
|
|
|
|
_iov_alloc_buf(&md_iov, 128 * 2);
|
|
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, 2, SPDK_DIF_GUARD_ERROR);
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, 2, SPDK_DIF_APPTAG_ERROR);
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, 2, SPDK_DIF_REFTAG_ERROR);
|
|
dix_inject_error_and_verify(iovs, 4, &md_iov, 4096, 128, 2, SPDK_DIF_DATA_ERROR);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
_iov_free_buf(&iovs[i]);
|
|
}
|
|
_iov_free_buf(&md_iov);
|
|
}
|
|
|
|
int
|
|
main(int argc, char **argv)
|
|
{
|
|
CU_pSuite suite = NULL;
|
|
unsigned int num_failures;
|
|
|
|
if (CU_initialize_registry() != CUE_SUCCESS) {
|
|
return CU_get_error();
|
|
}
|
|
|
|
suite = CU_add_suite("dif", NULL, NULL);
|
|
if (suite == NULL) {
|
|
CU_cleanup_registry();
|
|
return CU_get_error();
|
|
}
|
|
|
|
if (
|
|
CU_add_test(suite, "dif_generate_and_verify_test", dif_generate_and_verify_test) == NULL ||
|
|
CU_add_test(suite, "dif_disable_check_test", dif_disable_check_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_0_error_test", dif_sec_512_md_0_error_test) == NULL ||
|
|
CU_add_test(suite, "dif_guard_seed_test", dif_guard_seed_test) == NULL ||
|
|
CU_add_test(suite, "dif_disable_sec_512_md_8_single_iov_test",
|
|
dif_disable_sec_512_md_8_single_iov_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_0_single_iov_test",
|
|
dif_sec_512_md_8_prchk_0_single_iov_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_0_1_2_4_multi_iovs_test",
|
|
dif_sec_512_md_8_prchk_0_1_2_4_multi_iovs_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_prchk_7_multi_iovs_test",
|
|
dif_sec_4096_md_128_prchk_7_multi_iovs_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_7_multi_iovs_split_data_and_md_test",
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_data_and_md_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_7_multi_iovs_split_data_test",
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_data_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_7_multi_iovs_split_guard_test",
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_guard_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_7_multi_iovs_split_apptag_test",
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_apptag_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_7_multi_iovs_split_reftag_test",
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_split_reftag_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_512_md_8_prchk_7_multi_iovs_complex_splits_test",
|
|
dif_sec_512_md_8_prchk_7_multi_iovs_complex_splits_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_prchk_7_multi_iovs_complex_splits_test",
|
|
dif_sec_4096_md_128_prchk_7_multi_iovs_complex_splits_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test",
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_data_and_md_test",
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_data_and_md_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_data_test",
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_data_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_guard_test",
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_guard_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_inject_1_2_4_8__multi_iovs_split_apptag_test",
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_apptag_test) == NULL ||
|
|
CU_add_test(suite, "dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_reftag_test",
|
|
dif_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_reftag_test) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_512_md_8_prchk_0_single_iov",
|
|
dif_copy_sec_512_md_8_prchk_0_single_iov) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_512_md_8_prchk_0_1_2_4_multi_iovs",
|
|
dif_copy_sec_512_md_8_prchk_0_1_2_4_multi_iovs) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_4096_md_128_prchk_7_multi_iovs",
|
|
dif_copy_sec_4096_md_128_prchk_7_multi_iovs) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_512_md_8_prchk_7_multi_iovs_split_data",
|
|
dif_copy_sec_512_md_8_prchk_7_multi_iovs_split_data) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_512_md_8_prchk_7_multi_iovs_complex_splits",
|
|
dif_copy_sec_512_md_8_prchk_7_multi_iovs_complex_splits) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test",
|
|
dif_copy_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test) == NULL ||
|
|
CU_add_test(suite, "dif_copy_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_test",
|
|
dif_copy_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_test) == NULL ||
|
|
CU_add_test(suite, "dix_sec_512_md_0_error", dix_sec_512_md_0_error) == NULL ||
|
|
CU_add_test(suite, "dix_sec_512_md_8_prchk_0_single_iov",
|
|
dix_sec_512_md_8_prchk_0_single_iov) == NULL ||
|
|
CU_add_test(suite, "dix_sec_512_md_8_prchk_0_1_2_4_multi_iovs",
|
|
dix_sec_512_md_8_prchk_0_1_2_4_multi_iovs) == NULL ||
|
|
CU_add_test(suite, "dix_sec_4096_md_128_prchk_7_multi_iovs",
|
|
dix_sec_4096_md_128_prchk_7_multi_iovs) == NULL ||
|
|
CU_add_test(suite, "dix_sec_512_md_8_prchk_7_multi_iovs_split_data",
|
|
dix_sec_512_md_8_prchk_7_multi_iovs_split_data) == NULL ||
|
|
CU_add_test(suite, "dix_sec_512_md_8_prchk_7_multi_iovs_complex_splits",
|
|
dix_sec_512_md_8_prchk_7_multi_iovs_complex_splits) == NULL ||
|
|
CU_add_test(suite, "dix_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test",
|
|
dix_sec_4096_md_128_inject_1_2_4_8_multi_iovs_test) == NULL ||
|
|
CU_add_test(suite, "dix_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_test",
|
|
dix_sec_4096_md_128_inject_1_2_4_8_multi_iovs_split_test) == NULL
|
|
) {
|
|
CU_cleanup_registry();
|
|
return CU_get_error();
|
|
}
|
|
|
|
CU_basic_set_mode(CU_BRM_VERBOSE);
|
|
|
|
CU_basic_run_tests();
|
|
|
|
num_failures = CU_get_number_of_failures();
|
|
CU_cleanup_registry();
|
|
|
|
return num_failures;
|
|
}
|