Changpeng Liu 3b6622046e nvme/pcie: use 16 bits width access API for PCI_COMMAND register ... PCI_COMMAND register with offset 0x4 is 16 bits width. Change-Id: I86483e58a3ac680efaae6ff7edaadde8efc289f6 Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/2589 Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com> Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>		2020-05-29 14:59:24 +00:00
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.gitignore	test: move NVMe library tests to test/unit	2017-06-21 16:51:12 -04:00
Makefile	build: make nvme.unittest.mk the common unittest .mk include	2018-02-14 10:40:40 -05:00
nvme_pcie_ut.c	nvme/pcie: use 16 bits width access API for PCI_COMMAND register	2020-05-29 14:59:24 +00:00