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nvme: separate nvme_ctrlr_start() into different functions

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Currently in the function nvme_ctrlr_start() the initialization
process is executed as a whole, in the case there are many controllers
in one system, which means other controllers must call the function
one by one.  While here, we add several states here, which can
help refactoring the initialization process.

Change-Id: I209cf964bbf6e151823a7ecdc6a3f6e6e69df297
Signed-off-by: Changpeng Liu <changpeng.liu@intel.com>
Reviewed-on: https://review.gerrithub.io/424157
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
This commit is contained in:
Changpeng Liu 2018-09-06 01:25:16 -04:00 committed by Jim Harris
parent cd9518e11b
commit eb5cb3db16
5 changed files with 183 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/nvme/nvme.c
View File

@ -406,8 +406,8 @@ nvme_init_controllers(void *cb_ctx, spdk_nvme_attach_cb attach_cb)
while (!TAILQ_EMPTY(&g_nvme_init_ctrlrs)) {
TAILQ_FOREACH_SAFE(ctrlr, &g_nvme_init_ctrlrs, tailq, ctrlr_tmp) {
/* Drop the driver lock while calling nvme_ctrlr_process_init()
* since it needs to acquire the driver lock internally when calling
* nvme_ctrlr_start().
* since it needs to acquire the driver lock internally when initializing
* controller.
*
* TODO: Rethink the locking - maybe reset should take the lock so that start() and
* the functions it calls (in particular nvme_ctrlr_set_num_qpairs())

136
lib/nvme/nvme_ctrlr.c
View File

@ -41,8 +41,6 @@
static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
struct nvme_async_event_request *aer);
static int nvme_ctrlr_start(struct spdk_nvme_ctrlr *ctrlr);
static int
nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
{
@ -618,6 +616,26 @@ nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
return "enable controller by writing CC.EN = 1";
case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
return "wait for CSTS.RDY = 1";
case NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE:
return "enable admin queue";
case NVME_CTRLR_STATE_IDENTIFY:
return "identify controller";
case NVME_CTRLR_STATE_SET_NUM_QPAIRS:
return "set number of queues";
case NVME_CTRLR_STATE_CONSTRUCT_NS:
return "construct namespaces";
case NVME_CTRLR_STATE_CONFIGURE_AER:
return "configure AER";
case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
return "set supported log pages";
case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
return "set supported features";
case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
return "set doorbell buffer config";
case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
return "set keep alive timeout";
case NVME_CTRLR_STATE_SET_HOST_ID:
return "set host ID";
case NVME_CTRLR_STATE_READY:
return "ready";
}
@ -1567,7 +1585,7 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
union spdk_nvme_cc_register cc;
union spdk_nvme_csts_register csts;
uint32_t ready_timeout_in_ms;
int rc;
int rc = 0;
/*
* May need to avoid accessing any register on the target controller
@ -1685,14 +1703,63 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
SPDK_DEBUGLOG(SPDK_LOG_NVME, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
/*
* The controller has been enabled.
* Perform the rest of initialization in nvme_ctrlr_start() serially.
* Perform the rest of initialization serially.
*/
rc = nvme_ctrlr_start(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
return rc;
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE, NVME_TIMEOUT_INFINITE);
return 0;
}
break;
case NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE:
nvme_ctrlr_enable_admin_queue(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_IDENTIFY:
rc = nvme_ctrlr_identify(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QPAIRS, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_SET_NUM_QPAIRS:
rc = nvme_ctrlr_set_num_qpairs(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONSTRUCT_NS, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_CONSTRUCT_NS:
rc = nvme_ctrlr_construct_namespaces(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_CONFIGURE_AER:
rc = nvme_ctrlr_configure_aer(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
nvme_ctrlr_set_supported_features(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_SET_HOST_ID:
rc = nvme_ctrlr_set_host_id(ctrlr);
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
break;
case NVME_CTRLR_STATE_READY:
SPDK_DEBUGLOG(SPDK_LOG_NVME, "Ctrlr already in ready state\n");
return 0;
@ -1711,60 +1778,7 @@ init_timeout:
return -1;
}
return 0;
}
static int
nvme_ctrlr_start(struct spdk_nvme_ctrlr *ctrlr)
{
int rc;
nvme_ctrlr_enable_admin_queue(ctrlr);
rc = nvme_ctrlr_identify(ctrlr);
if (rc) {
return rc;
}
rc = nvme_ctrlr_set_num_qpairs(ctrlr);
if (rc) {
return rc;
}
rc = nvme_ctrlr_construct_namespaces(ctrlr);
if (rc) {
return rc;
}
rc = nvme_ctrlr_configure_aer(ctrlr);
if (rc) {
return rc;
}
rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
if (rc) {
return rc;
}
nvme_ctrlr_set_supported_features(ctrlr);
rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
if (rc) {
return rc;
}
rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
if (rc) {
SPDK_ERRLOG("Setting keep alive timeout failed\n");
return rc;
}
rc = nvme_ctrlr_set_host_id(ctrlr);
if (rc) {
return rc;
}
return 0;
return rc;
}
int

50
lib/nvme/nvme_internal.h
View File

@ -412,6 +412,56 @@ enum nvme_ctrlr_state {
*/
NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
/**
* Enable the Admin queue of the controller.
*/
NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE,
/**
* Identify Controller command will be sent to then controller.
*/
NVME_CTRLR_STATE_IDENTIFY,
/**
* Setup Number of Queues of the controller.
*/
NVME_CTRLR_STATE_SET_NUM_QPAIRS,
/**
* Construct Namespaces of the controller.
*/
NVME_CTRLR_STATE_CONSTRUCT_NS,
/**
* Configure AER of the controller.
*/
NVME_CTRLR_STATE_CONFIGURE_AER,
/**
* Set supported log pages of the controller.
*/
NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
/**
* Set supported features of the controller.
*/
NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
/**
* Set Doorbell Buffer Config of the controller.
*/
NVME_CTRLR_STATE_SET_DB_BUF_CFG,
/**
* Set Keep Alive Timeout of the controller.
*/
NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT,
/**
* Set Host ID of the controller.
*/
NVME_CTRLR_STATE_SET_HOST_ID,
/**
* Controller initialization has completed and the controller is ready.
*/

3
test/unit/lib/nvme/nvme.c/nvme_ut.c
View File

@ -65,9 +65,6 @@ DEFINE_STUB(nvme_ctrlr_add_process, int,
DEFINE_STUB(nvme_ctrlr_process_init, int,
(struct spdk_nvme_ctrlr *ctrlr), 0)
DEFINE_STUB(nvme_ctrlr_start, int,
(struct spdk_nvme_ctrlr *ctrlr), 0)
DEFINE_STUB(spdk_pci_device_get_addr, struct spdk_pci_addr,
(struct spdk_pci_device *pci_dev), {0})

63
test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c
View File

@ -475,7 +475,14 @@ test_nvme_ctrlr_init_en_1_rdy_0(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);
@ -522,7 +529,14 @@ test_nvme_ctrlr_init_en_1_rdy_1(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);
@ -690,7 +704,14 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);
@ -860,7 +881,14 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);
@ -1029,7 +1057,14 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);
@ -1068,7 +1103,14 @@ test_nvme_ctrlr_init_en_0_rdy_0(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);
@ -1113,7 +1155,14 @@ test_nvme_ctrlr_init_en_0_rdy_1(void)
*/
g_ut_nvme_regs.csts.bits.rdy = 1;
CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_ADMIN_QUEUE);
/*
* Transition to READY.
*/
while (ctrlr.state != NVME_CTRLR_STATE_READY) {
nvme_ctrlr_process_init(&ctrlr);
}
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
nvme_ctrlr_destruct(&ctrlr);