From e8c8d4ebc7e49385d9ba75b39d340722ff3ec0b9 Mon Sep 17 00:00:00 2001 From: Mao Jiang Date: Fri, 21 May 2021 15:19:50 +0800 Subject: [PATCH] test/pcie_common: cases for connecting qpair Change-Id: If03ff8d382c663d1f1e291a2e9c84e7c0b1cd7a9 Signed-off-by: Mao Jiang Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/7994 Tested-by: SPDK CI Jenkins Reviewed-by: Changpeng Liu Reviewed-by: Aleksey Marchuk Reviewed-by: Ben Walker Community-CI: Mellanox Build Bot --- .../nvme_pcie_common.c/nvme_pcie_common_ut.c | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/test/unit/lib/nvme/nvme_pcie_common.c/nvme_pcie_common_ut.c b/test/unit/lib/nvme/nvme_pcie_common.c/nvme_pcie_common_ut.c index 7c5f8152b..bdc137516 100644 --- a/test/unit/lib/nvme/nvme_pcie_common.c/nvme_pcie_common_ut.c +++ b/test/unit/lib/nvme/nvme_pcie_common.c/nvme_pcie_common_ut.c @@ -287,6 +287,146 @@ test_nvme_pcie_ctrlr_cmd_create_delete_io_queue(void) CU_ASSERT(rc == -ENOMEM); } +static void +test_nvme_pcie_ctrlr_connect_qpair(void) +{ + struct nvme_pcie_ctrlr pctrlr = {}; + struct nvme_pcie_qpair pqpair = {}; + struct spdk_nvme_transport_poll_group poll_group = {}; + struct spdk_nvme_cpl cpl = {}; + struct spdk_nvme_qpair adminq = {}; + struct nvme_request req[2] = {}; + int rc; + + pqpair.cpl = &cpl; + pqpair.num_entries = 1; + pqpair.qpair.ctrlr = &pctrlr.ctrlr; + pqpair.qpair.id = 1; + pqpair.num_entries = 1; + pqpair.cpl_bus_addr = 0xDEADBEEF; + pqpair.cmd_bus_addr = 0xDDADBEEF; + pqpair.qpair.qprio = SPDK_NVME_QPRIO_HIGH; + pqpair.stat = NULL; + pqpair.qpair.poll_group = &poll_group; + pctrlr.ctrlr.page_size = 4096; + + /* Shadow doorbell available */ + pctrlr.doorbell_stride_u32 = 1; + pctrlr.ctrlr.shadow_doorbell = spdk_zmalloc(pctrlr.ctrlr.page_size, pctrlr.ctrlr.page_size, + NULL, SPDK_ENV_LCORE_ID_ANY, + SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE); + pctrlr.ctrlr.eventidx = spdk_zmalloc(pctrlr.ctrlr.page_size, pctrlr.ctrlr.page_size, + NULL, SPDK_ENV_LCORE_ID_ANY, + SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE); + pctrlr.ctrlr.adminq = &adminq; + STAILQ_INIT(&pctrlr.ctrlr.adminq->free_req); + for (int i = 0; i < 2; i++) { + STAILQ_INSERT_HEAD(&pctrlr.ctrlr.adminq->free_req, &req[i], stailq); + } + + rc = nvme_pcie_ctrlr_connect_qpair(&pctrlr.ctrlr, &pqpair.qpair); + CU_ASSERT(rc == 0); + CU_ASSERT(req[0].cmd.opc == SPDK_NVME_OPC_CREATE_IO_SQ); + CU_ASSERT(req[0].cmd.cdw10_bits.create_io_q.qid == 1); + CU_ASSERT(req[0].cmd.cdw10_bits.create_io_q.qsize == 0); + CU_ASSERT(req[0].cmd.cdw11_bits.create_io_sq.pc == 1); + CU_ASSERT(req[0].cmd.cdw11_bits.create_io_sq.qprio == SPDK_NVME_QPRIO_HIGH); + CU_ASSERT(req[0].cmd.cdw11_bits.create_io_sq.cqid = 1); + CU_ASSERT(req[0].cmd.dptr.prp.prp1 == 0xDDADBEEF); + CU_ASSERT(req[1].cmd.opc == SPDK_NVME_OPC_CREATE_IO_CQ); + CU_ASSERT(req[1].cmd.cdw10_bits.create_io_q.qid == 1); + CU_ASSERT(req[1].cmd.cdw10_bits.create_io_q.qsize == 0); + CU_ASSERT(req[1].cmd.cdw11_bits.create_io_cq.pc == 1); + CU_ASSERT(req[1].cmd.dptr.prp.prp1 == 0xDEADBEEF); + /* doorbell stride and qid are 1 */ + CU_ASSERT(pqpair.shadow_doorbell.sq_tdbl == pctrlr.ctrlr.shadow_doorbell + 2); + CU_ASSERT(pqpair.shadow_doorbell.cq_hdbl == pctrlr.ctrlr.shadow_doorbell + 3); + CU_ASSERT(pqpair.shadow_doorbell.sq_eventidx == pctrlr.ctrlr.eventidx + 2); + CU_ASSERT(pqpair.shadow_doorbell.cq_eventidx == pctrlr.ctrlr.eventidx + 3); + CU_ASSERT(pqpair.flags.has_shadow_doorbell == 1); + CU_ASSERT(STAILQ_EMPTY(&pctrlr.ctrlr.adminq->free_req)); + + spdk_free(pctrlr.ctrlr.shadow_doorbell); + spdk_free(pctrlr.ctrlr.eventidx); + pctrlr.ctrlr.shadow_doorbell = NULL; + pctrlr.ctrlr.eventidx = NULL; + + /* Shadow doorbell 0 */ + memset(req, 0, sizeof(struct nvme_request) * 2); + memset(&pqpair, 0, sizeof(pqpair)); + pqpair.cpl = &cpl; + pqpair.qpair.ctrlr = &pctrlr.ctrlr; + pqpair.qpair.id = 1; + pqpair.num_entries = 1; + pqpair.cpl_bus_addr = 0xDEADBEEF; + pqpair.cmd_bus_addr = 0xDDADBEEF; + pqpair.qpair.qprio = SPDK_NVME_QPRIO_HIGH; + pqpair.stat = NULL; + pqpair.qpair.poll_group = &poll_group; + for (int i = 0; i < 2; i++) { + STAILQ_INSERT_HEAD(&pctrlr.ctrlr.adminq->free_req, &req[i], stailq); + } + + rc = nvme_pcie_ctrlr_connect_qpair(&pctrlr.ctrlr, &pqpair.qpair); + CU_ASSERT(rc == 0); + CU_ASSERT(req[0].cmd.opc == SPDK_NVME_OPC_CREATE_IO_SQ); + CU_ASSERT(req[0].cmd.cdw10_bits.create_io_q.qid == 1); + CU_ASSERT(req[0].cmd.cdw10_bits.create_io_q.qsize == 0); + CU_ASSERT(req[0].cmd.cdw11_bits.create_io_sq.pc == 1); + CU_ASSERT(req[0].cmd.cdw11_bits.create_io_sq.qprio == SPDK_NVME_QPRIO_HIGH); + CU_ASSERT(req[0].cmd.cdw11_bits.create_io_sq.cqid = 1); + CU_ASSERT(req[0].cmd.dptr.prp.prp1 == 0xDDADBEEF); + CU_ASSERT(req[1].cmd.opc == SPDK_NVME_OPC_CREATE_IO_CQ); + CU_ASSERT(req[1].cmd.cdw10_bits.create_io_q.qid == 1); + CU_ASSERT(req[1].cmd.cdw10_bits.create_io_q.qsize == 0); + CU_ASSERT(req[1].cmd.cdw11_bits.create_io_cq.pc == 1); + CU_ASSERT(req[1].cmd.dptr.prp.prp1 == 0xDEADBEEF); + CU_ASSERT(pqpair.shadow_doorbell.sq_tdbl == NULL); + CU_ASSERT(pqpair.shadow_doorbell.sq_eventidx == NULL); + CU_ASSERT(pqpair.flags.has_shadow_doorbell == 0); + CU_ASSERT(STAILQ_EMPTY(&pctrlr.ctrlr.adminq->free_req)); + + /* Completion error */ + memset(req, 0, sizeof(struct nvme_request) * 2); + memset(&pqpair, 0, sizeof(pqpair)); + pqpair.cpl = &cpl; + pqpair.qpair.ctrlr = &pctrlr.ctrlr; + pqpair.qpair.id = 1; + pqpair.num_entries = 1; + pqpair.cpl_bus_addr = 0xDEADBEEF; + pqpair.cmd_bus_addr = 0xDDADBEEF; + pqpair.qpair.qprio = SPDK_NVME_QPRIO_HIGH; + pqpair.stat = NULL; + pqpair.qpair.poll_group = &poll_group; + for (int i = 0; i < 2; i++) { + STAILQ_INSERT_HEAD(&pctrlr.ctrlr.adminq->free_req, &req[i], stailq); + } + MOCK_SET(nvme_wait_for_completion, -EIO); + + rc = nvme_pcie_ctrlr_connect_qpair(&pctrlr.ctrlr, &pqpair.qpair); + CU_ASSERT(rc == -1); + /* Remove unused request */ + STAILQ_REMOVE_HEAD(&pctrlr.ctrlr.adminq->free_req, stailq); + CU_ASSERT(STAILQ_EMPTY(&pctrlr.ctrlr.adminq->free_req)); + MOCK_CLEAR(nvme_wait_for_completion); + + /* No available request used */ + memset(req, 0, sizeof(struct nvme_request) * 2); + memset(&pqpair, 0, sizeof(pqpair)); + pqpair.cpl = &cpl; + pqpair.qpair.ctrlr = &pctrlr.ctrlr; + pqpair.qpair.id = 1; + pqpair.num_entries = 1; + pqpair.cpl_bus_addr = 0xDEADBEEF; + pqpair.cmd_bus_addr = 0xDDADBEEF; + pqpair.qpair.qprio = SPDK_NVME_QPRIO_HIGH; + pqpair.stat = NULL; + pqpair.qpair.poll_group = &poll_group; + + rc = nvme_pcie_ctrlr_connect_qpair(&pctrlr.ctrlr, &pqpair.qpair); + CU_ASSERT(rc == -ENOMEM); +} + int main(int argc, char **argv) { CU_pSuite suite = NULL; @@ -299,6 +439,7 @@ int main(int argc, char **argv) CU_ADD_TEST(suite, test_nvme_pcie_ctrlr_alloc_cmb); CU_ADD_TEST(suite, test_nvme_pcie_qpair_construct_destroy); CU_ADD_TEST(suite, test_nvme_pcie_ctrlr_cmd_create_delete_io_queue); + CU_ADD_TEST(suite, test_nvme_pcie_ctrlr_connect_qpair); CU_basic_set_mode(CU_BRM_VERBOSE); CU_basic_run_tests();