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nvme_spec: declare CSTS with the correct type

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nvme_spec.h already has a structure with the correct bitfields for the
CSTS register, so use it in struct spdk_nvme_registers.

Change-Id: Id0663aee2611fb5195f9012a3176799e32701bb0
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
This commit is contained in:
Daniel Verkamp 2016-03-01 16:28:29 -07:00 committed by Gerrit Code Review
parent 8acc50fc05
commit e20639540e
2 changed files with 7 additions and 7 deletions
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2
include/spdk/nvme_spec.h
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@ -242,7 +242,7 @@ struct spdk_nvme_registers {
union spdk_nvme_cc_register cc; union spdk_nvme_cc_register cc;
uint32_t reserved1; uint32_t reserved1;
uint32_t csts; /* controller status */ union spdk_nvme_csts_register csts; /* controller status */
uint32_t nssr; /* NVM subsystem reset */ uint32_t nssr; /* NVM subsystem reset */
/** admin queue attributes */ /** admin queue attributes */

12
lib/nvme/nvme_ctrlr.c
View File

@ -258,7 +258,7 @@ nvme_ctrlr_wait_for_ready(struct spdk_nvme_ctrlr *ctrlr, int desired_ready_value
cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo.raw); cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo.raw);
ready_timeout_in_ms = cap_lo.bits.to * 500; ready_timeout_in_ms = cap_lo.bits.to * 500;
csts.raw = nvme_mmio_read_4(ctrlr, csts); csts.raw = nvme_mmio_read_4(ctrlr, csts.raw);
ms_waited = 0; ms_waited = 0;
@ -269,7 +269,7 @@ nvme_ctrlr_wait_for_ready(struct spdk_nvme_ctrlr *ctrlr, int desired_ready_value
"within %d ms\n", desired_ready_value, ready_timeout_in_ms); "within %d ms\n", desired_ready_value, ready_timeout_in_ms);
return ENXIO; return ENXIO;
} }
csts.raw = nvme_mmio_read_4(ctrlr, csts); csts.raw = nvme_mmio_read_4(ctrlr, csts.raw);
} }
return 0; return 0;
@ -282,7 +282,7 @@ nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
union spdk_nvme_csts_register csts; union spdk_nvme_csts_register csts;
cc.raw = nvme_mmio_read_4(ctrlr, cc.raw); cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
csts.raw = nvme_mmio_read_4(ctrlr, csts); csts.raw = nvme_mmio_read_4(ctrlr, csts.raw);
if (cc.bits.en == 1 && csts.bits.rdy == 0) { if (cc.bits.en == 1 && csts.bits.rdy == 0) {
nvme_ctrlr_wait_for_ready(ctrlr, 1); nvme_ctrlr_wait_for_ready(ctrlr, 1);
@ -305,7 +305,7 @@ nvme_ctrlr_shutdown(struct spdk_nvme_ctrlr *ctrlr)
cc.bits.shn = SPDK_NVME_SHN_NORMAL; cc.bits.shn = SPDK_NVME_SHN_NORMAL;
nvme_mmio_write_4(ctrlr, cc.raw, cc.raw); nvme_mmio_write_4(ctrlr, cc.raw, cc.raw);
csts.raw = nvme_mmio_read_4(ctrlr, csts); csts.raw = nvme_mmio_read_4(ctrlr, csts.raw);
/* /*
* The NVMe spec does not define a timeout period * The NVMe spec does not define a timeout period
* for shutdown notification, so we just pick * for shutdown notification, so we just pick
@ -314,7 +314,7 @@ nvme_ctrlr_shutdown(struct spdk_nvme_ctrlr *ctrlr)
*/ */
while (csts.bits.shst != SPDK_NVME_SHST_COMPLETE) { while (csts.bits.shst != SPDK_NVME_SHST_COMPLETE) {
nvme_delay(1000); nvme_delay(1000);
csts.raw = nvme_mmio_read_4(ctrlr, csts); csts.raw = nvme_mmio_read_4(ctrlr, csts.raw);
if (ms_waited++ >= 5000) if (ms_waited++ >= 5000)
break; break;
} }
@ -728,7 +728,7 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
int rc; int rc;
cc.raw = nvme_mmio_read_4(ctrlr, cc.raw); cc.raw = nvme_mmio_read_4(ctrlr, cc.raw);
csts.raw = nvme_mmio_read_4(ctrlr, csts); csts.raw = nvme_mmio_read_4(ctrlr, csts.raw);
cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo.raw); cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo.raw);
ready_timeout_in_ms = 500 * cap_lo.bits.to; ready_timeout_in_ms = 500 * cap_lo.bits.to;