diff --git a/lib/nvme/nvme_ctrlr.c b/lib/nvme/nvme_ctrlr.c index e9a799fa8..20653d6c5 100644 --- a/lib/nvme/nvme_ctrlr.c +++ b/lib/nvme/nvme_ctrlr.c @@ -1134,6 +1134,8 @@ nvme_ctrlr_state_string(enum nvme_ctrlr_state state) switch (state) { case NVME_CTRLR_STATE_INIT_DELAY: return "delay init"; + case NVME_CTRLR_STATE_READ_VS: + return "read vs"; case NVME_CTRLR_STATE_CHECK_EN: return "check en"; case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1: @@ -3124,7 +3126,12 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) } break; - case NVME_CTRLR_STATE_CHECK_EN: /* synonymous with NVME_CTRLR_STATE_INIT */ + case NVME_CTRLR_STATE_READ_VS: /* synonymous with NVME_CTRLR_STATE_INIT */ + nvme_ctrlr_get_vs(ctrlr, &ctrlr->vs); + nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE); + break; + + case NVME_CTRLR_STATE_CHECK_EN: /* Begin the hardware initialization by making sure the controller is disabled. */ if (cc.bits.en) { NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n"); @@ -3405,11 +3412,9 @@ nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr) /* This function should be called once at ctrlr initialization to set up constant properties. */ void -nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cap_register *cap, - const union spdk_nvme_vs_register *vs) +nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cap_register *cap) { ctrlr->cap = *cap; - ctrlr->vs = *vs; if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) { ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED; diff --git a/lib/nvme/nvme_internal.h b/lib/nvme/nvme_internal.h index e3b4ed8db..d41db35a8 100644 --- a/lib/nvme/nvme_internal.h +++ b/lib/nvme/nvme_internal.h @@ -518,14 +518,19 @@ enum nvme_ctrlr_state { NVME_CTRLR_STATE_INIT_DELAY, /** - * Check EN to prepare for controller initialization. + * Read Version (VS) register. */ - NVME_CTRLR_STATE_CHECK_EN, + NVME_CTRLR_STATE_READ_VS, /** * Controller has not started initialized yet. */ - NVME_CTRLR_STATE_INIT = NVME_CTRLR_STATE_CHECK_EN, + NVME_CTRLR_STATE_INIT = NVME_CTRLR_STATE_READ_VS, + + /** + * Check EN to prepare for controller initialization. + */ + NVME_CTRLR_STATE_CHECK_EN, /** * Waiting for CSTS.RDY to transition from 0 to 1 so that CC.EN may be set to 0. @@ -1037,8 +1042,7 @@ int nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register int nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz); int nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap); bool nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr); -void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cap_register *cap, - const union spdk_nvme_vs_register *vs); +void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cap_register *cap); void nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_cpl *cpl); void nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair); diff --git a/lib/nvme/nvme_pcie.c b/lib/nvme/nvme_pcie.c index 2a5a7f72d..d54602eea 100644 --- a/lib/nvme/nvme_pcie.c +++ b/lib/nvme/nvme_pcie.c @@ -908,7 +908,6 @@ static struct spdk_nvme_ctrlr *nvme_pcie_ctrlr_construct(const struct spdk_nvme_ struct spdk_pci_device *pci_dev = devhandle; struct nvme_pcie_ctrlr *pctrlr; union spdk_nvme_cap_register cap; - union spdk_nvme_vs_register vs; uint16_t cmd_reg; int rc; struct spdk_pci_id pci_id; @@ -960,14 +959,7 @@ static struct spdk_nvme_ctrlr *nvme_pcie_ctrlr_construct(const struct spdk_nvme_ return NULL; } - if (nvme_ctrlr_get_vs(&pctrlr->ctrlr, &vs)) { - SPDK_ERRLOG("get_vs() failed\n"); - spdk_pci_device_unclaim(pci_dev); - spdk_free(pctrlr); - return NULL; - } - - nvme_ctrlr_init_cap(&pctrlr->ctrlr, &cap, &vs); + nvme_ctrlr_init_cap(&pctrlr->ctrlr, &cap); /* Doorbell stride is 2 ^ (dstrd + 2), * but we want multiples of 4, so drop the + 2 */ diff --git a/lib/nvme/nvme_rdma.c b/lib/nvme/nvme_rdma.c index ab0b1d0c5..9061f7438 100644 --- a/lib/nvme/nvme_rdma.c +++ b/lib/nvme/nvme_rdma.c @@ -1739,7 +1739,6 @@ static struct spdk_nvme_ctrlr *nvme_rdma_ctrlr_construct(const struct spdk_nvme_ { struct nvme_rdma_ctrlr *rctrlr; union spdk_nvme_cap_register cap; - union spdk_nvme_vs_register vs; struct ibv_context **contexts; struct ibv_device_attr dev_attr; int i, flag, rc; @@ -1838,17 +1837,12 @@ static struct spdk_nvme_ctrlr *nvme_rdma_ctrlr_construct(const struct spdk_nvme_ goto destruct_ctrlr; } - if (nvme_ctrlr_get_vs(&rctrlr->ctrlr, &vs)) { - SPDK_ERRLOG("get_vs() failed\n"); - goto destruct_ctrlr; - } - if (nvme_ctrlr_add_process(&rctrlr->ctrlr, 0) != 0) { SPDK_ERRLOG("nvme_ctrlr_add_process() failed\n"); goto destruct_ctrlr; } - nvme_ctrlr_init_cap(&rctrlr->ctrlr, &cap, &vs); + nvme_ctrlr_init_cap(&rctrlr->ctrlr, &cap); SPDK_DEBUGLOG(nvme, "successfully initialized the nvmf ctrlr\n"); return &rctrlr->ctrlr; diff --git a/lib/nvme/nvme_tcp.c b/lib/nvme/nvme_tcp.c index 19ab9e933..27f3dceb7 100644 --- a/lib/nvme/nvme_tcp.c +++ b/lib/nvme/nvme_tcp.c @@ -1935,7 +1935,6 @@ static struct spdk_nvme_ctrlr *nvme_tcp_ctrlr_construct(const struct spdk_nvme_t { struct nvme_tcp_ctrlr *tctrlr; union spdk_nvme_cap_register cap; - union spdk_nvme_vs_register vs; int rc; tctrlr = calloc(1, sizeof(*tctrlr)); @@ -1975,19 +1974,13 @@ static struct spdk_nvme_ctrlr *nvme_tcp_ctrlr_construct(const struct spdk_nvme_t return NULL; } - if (nvme_ctrlr_get_vs(&tctrlr->ctrlr, &vs)) { - SPDK_ERRLOG("get_vs() failed\n"); - nvme_ctrlr_destruct(&tctrlr->ctrlr); - return NULL; - } - if (nvme_ctrlr_add_process(&tctrlr->ctrlr, 0) != 0) { SPDK_ERRLOG("nvme_ctrlr_add_process() failed\n"); nvme_ctrlr_destruct(&tctrlr->ctrlr); return NULL; } - nvme_ctrlr_init_cap(&tctrlr->ctrlr, &cap, &vs); + nvme_ctrlr_init_cap(&tctrlr->ctrlr, &cap); return &tctrlr->ctrlr; } diff --git a/lib/nvme/nvme_vfio_user.c b/lib/nvme/nvme_vfio_user.c index c674f9f5e..17a3de833 100644 --- a/lib/nvme/nvme_vfio_user.c +++ b/lib/nvme/nvme_vfio_user.c @@ -201,7 +201,6 @@ static struct spdk_nvme_ctrlr * struct nvme_pcie_ctrlr *pctrlr; uint16_t cmd_reg; union spdk_nvme_cap_register cap; - union spdk_nvme_vs_register vs; int ret; char ctrlr_path[PATH_MAX]; char ctrlr_bar0[PATH_MAX]; @@ -272,12 +271,7 @@ static struct spdk_nvme_ctrlr * goto exit; } - if (nvme_ctrlr_get_vs(&pctrlr->ctrlr, &vs)) { - SPDK_ERRLOG("get_vs() failed\n"); - goto exit; - } - - nvme_ctrlr_init_cap(&pctrlr->ctrlr, &cap, &vs); + nvme_ctrlr_init_cap(&pctrlr->ctrlr, &cap); /* Doorbell stride is 2 ^ (dstrd + 2), * but we want multiples of 4, so drop the + 2 */ pctrlr->doorbell_stride_u32 = 1 << cap.bits.dstrd; diff --git a/test/common/lib/nvme/common_stubs.h b/test/common/lib/nvme/common_stubs.h index 1dc22a162..5edb12994 100644 --- a/test/common/lib/nvme/common_stubs.h +++ b/test/common/lib/nvme/common_stubs.h @@ -74,8 +74,7 @@ DEFINE_STUB_V(nvme_ctrlr_destruct_finish, (struct spdk_nvme_ctrlr *ctrlr)); DEFINE_STUB(nvme_ctrlr_construct, int, (struct spdk_nvme_ctrlr *ctrlr), 0); DEFINE_STUB_V(nvme_ctrlr_destruct, (struct spdk_nvme_ctrlr *ctrlr)); DEFINE_STUB_V(nvme_ctrlr_init_cap, (struct spdk_nvme_ctrlr *ctrlr, - const union spdk_nvme_cap_register *cap, - const union spdk_nvme_vs_register *vs)); + const union spdk_nvme_cap_register *cap)); DEFINE_STUB(nvme_ctrlr_get_vs, int, (struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs), 0); DEFINE_STUB(nvme_ctrlr_get_cap, int, (struct spdk_nvme_ctrlr *ctrlr, diff --git a/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c b/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c index a11dbf000..9fb0bf8ba 100644 --- a/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c +++ b/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c @@ -623,6 +623,9 @@ test_nvme_ctrlr_init_en_1_rdy_0(void) ctrlr.cdata.nn = 1; ctrlr.page_size = 0x1000; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1); @@ -685,6 +688,9 @@ test_nvme_ctrlr_init_en_1_rdy_1(void) ctrlr.cdata.nn = 1; ctrlr.page_size = 0x1000; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -750,6 +756,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -781,6 +790,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -810,6 +822,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -839,6 +854,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -868,6 +886,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -925,6 +946,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -956,6 +980,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -987,6 +1014,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1016,6 +1046,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1045,6 +1078,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1101,6 +1137,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1132,6 +1171,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1161,6 +1203,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1192,6 +1237,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1221,6 +1269,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); @@ -1267,6 +1318,9 @@ test_nvme_ctrlr_init_en_0_rdy_0(void) ctrlr.cdata.nn = 1; ctrlr.page_size = 0x1000; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); @@ -1312,6 +1366,9 @@ test_nvme_ctrlr_init_en_0_rdy_1(void) ctrlr.cdata.nn = 1; ctrlr.page_size = 0x1000; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); @@ -2047,6 +2104,9 @@ test_nvme_ctrlr_init_delay(void) /* sleep timeout, start to initialize */ spdk_delay_us(2 * spdk_get_ticks_hz()); + while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + } CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); @@ -2719,9 +2779,10 @@ test_nvme_ctrlr_reset(void) SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); - ctrlr.vs.bits.mjr = 1; - ctrlr.vs.bits.mnr = 2; - ctrlr.vs.bits.ter = 0; + g_ut_nvme_regs.vs.bits.mjr = 1; + g_ut_nvme_regs.vs.bits.mnr = 2; + g_ut_nvme_regs.vs.bits.ter = 0; + nvme_ctrlr_get_vs(&ctrlr, &ctrlr.vs); ctrlr.cdata.nn = 2048; ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; @@ -2739,7 +2800,8 @@ test_nvme_ctrlr_reset(void) g_active_ns_list = active_ns_list2; g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq); - memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); + g_ut_nvme_regs.cc.raw = 0; + g_ut_nvme_regs.csts.raw = 0; g_set_reg_cb = check_en_set_rdy; CU_ASSERT(spdk_nvme_ctrlr_reset(&ctrlr) == 0); g_set_reg_cb = NULL;