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nvme: Modify the memory barrier mode to improve performance

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The mode of dmb oshld can guarantees cpu sequential execution,
which has less impact on performance.

Change-Id: If30b6a682a2216eecd1da039267ed4f5471afc38
Signed-off-by: h00448672 <heyang18@huawei.com>
Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/446827
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
This commit is contained in:
h00448672 2019-03-04 14:59:07 +08:00 committed by Darek Stojaczyk
parent 9e2eb8cb51
commit dc61452d6e
1 changed files with 3 additions and 1 deletions
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4
lib/nvme/nvme_pcie.c
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@ -2139,13 +2139,15 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
if (cpl->status.p != pqpair->flags.phase) {
break;
}
#if defined(__PPC64__) || defined(__aarch64__)
#ifdef __PPC64__
/*
* This memory barrier prevents reordering of:
* - load after store from/to tr
* - load after load cpl phase and cpl cid
*/
spdk_mb();
#elif defined(__aarch64__)
__asm volatile("dmb oshld" ::: "memory");
#endif
if (spdk_unlikely(++pqpair->cq_head == pqpair->num_entries)) {