lib/vmd: Removed typedefs from structures definitions
Removed typedefs and unused structures. Change-Id: I711094097520333cbeda2f26a1a7d403750070b1 Signed-off-by: Wojciech Malikowski <wojciech.malikowski@intel.com> Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/456479 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
This commit is contained in:
Wojciech Malikowski
Jim Harris
parent
f7e68be171
commit
d3a0531bc1
168
lib/vmd/vmd.c
168
lib/vmd/vmd.c
@ -57,21 +57,21 @@ struct vmd_container {
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uint32_t count;
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/* can target specific vmd or all vmd when null */
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struct spdk_pci_addr *vmd_target_addr;
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vmd_adapter vmd[MAX_VMD_SUPPORTED];
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struct vmd_adapter vmd[MAX_VMD_SUPPORTED];
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};
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static struct vmd_container g_vmd_container;
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static int g_end_device_count;
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static uint8_t g_end_device_count;
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static bool
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vmd_is_valid_cfg_addr(vmd_pci_bus *bus, uint64_t addr)
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vmd_is_valid_cfg_addr(struct vmd_pci_bus *bus, uint64_t addr)
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{
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return addr >= (uint64_t)bus->vmd->cfg_vaddr &&
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addr < bus->vmd->cfgbar_size + (uint64_t)bus->vmd->cfg_vaddr;
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}
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static void
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vmd_align_base_addrs(vmd_adapter *vmd, uint32_t alignment)
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vmd_align_base_addrs(struct vmd_adapter *vmd, uint32_t alignment)
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{
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uint32_t pad;
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/*
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@ -94,9 +94,10 @@ vmd_align_base_addrs(vmd_adapter *vmd, uint32_t alignment)
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* Consider increasing the size of vmd membar if 0x0 is returned.
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*/
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static uint64_t
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vmd_allocate_base_addr(vmd_adapter *vmd, vmd_pci_device *dev, uint32_t size)
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vmd_allocate_base_addr(struct vmd_adapter *vmd, struct vmd_pci_device *dev, uint32_t size)
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{
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uint64_t base_address = 0;
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struct vmd_pci_bus *hp_bus;
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if (size && ((size & (~size + 1)) != size)) {
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return base_address;
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@ -109,7 +110,7 @@ vmd_allocate_base_addr(vmd_adapter *vmd, vmd_pci_device *dev, uint32_t size)
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* get a buffer from the unused chunk. First fit algorithm, is used.
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*/
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if (dev) {
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vmd_pci_bus *hp_bus = vmd_is_dev_in_hotplug_path(dev);
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hp_bus = vmd_is_dev_in_hotplug_path(dev);
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if (hp_bus && hp_bus->self) {
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return vmd_hp_allocate_base_addr(hp_bus->self->hp, size);
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}
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@ -135,19 +136,24 @@ vmd_allocate_base_addr(vmd_adapter *vmd, vmd_pci_device *dev, uint32_t size)
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}
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static bool
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vmd_is_end_device(vmd_pci_device *dev)
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vmd_is_end_device(struct vmd_pci_device *dev)
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{
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return (dev && dev->header) &&
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((dev->header->common.header_type & ~PCI_MULTI_FUNCTION) == PCI_HEADER_TYPE_NORMAL);
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}
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static void
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vmd_update_base_limit_register(vmd_pci_device *dev, uint16_t base, uint16_t limit)
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vmd_update_base_limit_register(struct vmd_pci_device *dev, uint16_t base, uint16_t limit)
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{
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if (base && limit && dev != NULL) {
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vmd_pci_bus *bus = dev->parent;
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struct vmd_pci_bus *bus = dev->parent;
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struct vmd_pci_device *bridge;
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if (base == 0 || limit == 0) {
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return;
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}
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while (bus && bus->self != NULL) {
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vmd_pci_device *bridge = bus->self;
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bridge = bus->self;
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/* This is only for 32-bit memory space, need to revisit to support 64-bit */
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if (bridge->header->one.mem_base > base) {
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@ -159,20 +165,21 @@ vmd_update_base_limit_register(vmd_pci_device *dev, uint16_t base, uint16_t limi
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bridge->header->one.mem_limit = limit;
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limit = bridge->header->one.mem_limit;
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}
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bus = bus->parent;
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}
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}
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}
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static bool
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vmd_assign_base_addrs(vmd_pci_device *dev)
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vmd_assign_base_addrs(struct vmd_pci_device *dev)
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{
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uint16_t mem_base = 0, mem_limit = 0;
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unsigned char mem_attr = 0;
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int last = dev->header_type ? 2 : 6;
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vmd_adapter *vmd = NULL;
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struct vmd_adapter *vmd = NULL;
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bool ret_val = false;
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uint32_t bar_value;
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uint32_t table_offset;
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if (dev && dev->bus) {
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vmd = dev->bus->vmd;
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@ -201,7 +208,9 @@ vmd_assign_base_addrs(vmd_pci_device *dev)
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dev->header->zero.BAR[i] = (uint32_t)dev->bar[i].start;
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if (!dev->bar[i].start) {
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if (mem_attr == (PCI_BAR_MEMORY_PREFETCH | PCI_BAR_MEMORY_TYPE_64)) { i++; }
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if (mem_attr == (PCI_BAR_MEMORY_PREFETCH | PCI_BAR_MEMORY_TYPE_64)) {
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i++;
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}
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continue;
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}
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@ -228,9 +237,9 @@ vmd_assign_base_addrs(vmd_pci_device *dev)
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cmd++;
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if (dev->msix_cap && ret_val) {
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uint32_t table_offset = ((volatile pci_msix_cap *)dev->msix_cap)->msix_table_offset;
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table_offset = ((volatile struct pci_msix_cap *)dev->msix_cap)->msix_table_offset;
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if (dev->bar[table_offset & 0x3].vaddr) {
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dev->msix_table = (volatile pci_msix_table_entry *)
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dev->msix_table = (volatile struct pci_msix_table_entry *)
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(dev->bar[table_offset & 0x3].vaddr + (table_offset & 0xfff8));
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}
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}
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@ -243,12 +252,12 @@ vmd_assign_base_addrs(vmd_pci_device *dev)
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}
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static void
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vmd_get_device_capabilities(vmd_pci_device *dev)
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vmd_get_device_capabilities(struct vmd_pci_device *dev)
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{
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volatile uint8_t *config_space;
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uint8_t capabilities_offset;
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pci_capabilities_header *capabilities_hdr;
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struct pci_capabilities_header *capabilities_hdr;
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config_space = (volatile uint8_t *)dev->header;
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if ((dev->header->common.status & PCI_CAPABILITIES_LIST) == 0) {
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@ -261,18 +270,19 @@ vmd_get_device_capabilities(vmd_pci_device *dev)
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}
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while (capabilities_offset > 0) {
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capabilities_hdr = (pci_capabilities_header *)&config_space[capabilities_offset];
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capabilities_hdr = (struct pci_capabilities_header *)
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&config_space[capabilities_offset];
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switch (capabilities_hdr->capability_id) {
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case CAPABILITY_ID_PCI_EXPRESS:
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dev->pcie_cap = (volatile pci_express_cap *)(capabilities_hdr);
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dev->pcie_cap = (volatile struct pci_express_cap *)(capabilities_hdr);
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break;
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case CAPABILITY_ID_MSI:
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dev->msi_cap = (volatile pci_msi_cap *)capabilities_hdr;
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dev->msi_cap = (volatile struct pci_msi_cap *)capabilities_hdr;
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break;
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case CAPABILITY_ID_MSIX:
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dev->msix_cap = (volatile pci_msix_capability *)capabilities_hdr;
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dev->msix_cap = (volatile struct pci_msix_capability *)capabilities_hdr;
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dev->msix_table_size = dev->msix_cap->message_control.bit.table_size + 1;
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break;
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@ -283,16 +293,16 @@ vmd_get_device_capabilities(vmd_pci_device *dev)
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}
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}
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static volatile pci_enhanced_capability_header *
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vmd_get_enhanced_capabilities(vmd_pci_device *dev, uint16_t capability_id)
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static volatile struct pci_enhanced_capability_header *
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vmd_get_enhanced_capabilities(struct vmd_pci_device *dev, uint16_t capability_id)
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{
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uint8_t *data;
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uint16_t cap_offset = EXTENDED_CAPABILITY_OFFSET;
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volatile pci_enhanced_capability_header *cap_hdr = NULL;
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volatile struct pci_enhanced_capability_header *cap_hdr = NULL;
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data = (uint8_t *)dev->header;
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while (cap_offset >= EXTENDED_CAPABILITY_OFFSET) {
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cap_hdr = (volatile pci_enhanced_capability_header *) &data[cap_offset];
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cap_hdr = (volatile struct pci_enhanced_capability_header *) &data[cap_offset];
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if (cap_hdr->capability_id == capability_id) {
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return cap_hdr;
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}
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@ -306,7 +316,7 @@ vmd_get_enhanced_capabilities(vmd_pci_device *dev, uint16_t capability_id)
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}
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static void
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vmd_read_config_space(vmd_pci_device *dev)
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vmd_read_config_space(struct vmd_pci_device *dev)
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{
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/*
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* Writes to the pci config space is posted weite. To ensure transaction reaches its destination
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@ -316,19 +326,19 @@ vmd_read_config_space(vmd_pci_device *dev)
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{ uint16_t cmd = dev->header->common.command; (void)cmd; }
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vmd_get_device_capabilities(dev);
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dev->sn_cap = (serial_number_capability *)vmd_get_enhanced_capabilities(dev,
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dev->sn_cap = (struct serial_number_capability *)vmd_get_enhanced_capabilities(dev,
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DEVICE_SERIAL_NUMBER_CAP_ID);
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}
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static vmd_pci_device *
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vmd_alloc_dev(vmd_pci_bus *bus, uint32_t devfn)
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static struct vmd_pci_device *
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vmd_alloc_dev(struct vmd_pci_bus *bus, uint32_t devfn)
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{
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vmd_pci_device *dev = NULL;
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pci_header volatile *header;
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struct vmd_pci_device *dev = NULL;
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struct pci_header volatile *header;
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uint8_t header_type;
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uint32_t rev_class;
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header = (pci_header * volatile)(bus->vmd->cfg_vaddr +
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header = (struct pci_header * volatile)(bus->vmd->cfg_vaddr +
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CONFIG_OFFSET_ADDR(bus->bus_number, devfn, 0, 0));
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if (!vmd_is_valid_cfg_addr(bus, (uint64_t)header)) {
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return NULL;
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@ -341,7 +351,7 @@ vmd_alloc_dev(vmd_pci_bus *bus, uint32_t devfn)
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SPDK_DEBUGLOG(SPDK_LOG_VMD, "PCI device found: %04x:%04x ***\n",
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header->common.vendor_id, header->common.device_id);
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dev = calloc(1, sizeof(vmd_pci_device));
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dev = calloc(1, sizeof(*dev));
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if (!dev) {
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return NULL;
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}
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@ -375,9 +385,9 @@ vmd_alloc_dev(vmd_pci_bus *bus, uint32_t devfn)
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}
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static void
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vmd_add_bus_to_list(vmd_adapter *vmd, vmd_pci_bus *bus)
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vmd_add_bus_to_list(struct vmd_adapter *vmd, struct vmd_pci_bus *bus)
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{
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vmd_pci_bus *blist;
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struct vmd_pci_bus *blist;
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blist = vmd->bus_list;
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bus->next = NULL;
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@ -394,9 +404,9 @@ vmd_add_bus_to_list(vmd_adapter *vmd, vmd_pci_bus *bus)
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}
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static void
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vmd_pcibus_remove_device(vmd_pci_bus *bus, vmd_pci_device *device)
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vmd_pcibus_remove_device(struct vmd_pci_bus *bus, struct vmd_pci_device *device)
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{
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vmd_pci_device *list = bus->dev_list;
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struct vmd_pci_device *list = bus->dev_list;
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if (list == device) {
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bus->dev_list = NULL;
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@ -413,9 +423,9 @@ vmd_pcibus_remove_device(vmd_pci_bus *bus, vmd_pci_device *device)
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static bool
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vmd_bus_add_device(vmd_pci_bus *bus, vmd_pci_device *device)
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vmd_bus_add_device(struct vmd_pci_bus *bus, struct vmd_pci_device *device)
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{
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vmd_pci_device *next_dev = bus->dev_list;
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struct vmd_pci_device *next_dev = bus->dev_list;
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device->next = NULL;
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if (next_dev == NULL) {
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@ -432,12 +442,12 @@ vmd_bus_add_device(vmd_pci_bus *bus, vmd_pci_device *device)
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return 1;
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}
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static vmd_pci_bus *
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vmd_create_new_bus(vmd_pci_bus *parent, vmd_pci_device *bridge, uint8_t bus_number)
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static struct vmd_pci_bus *
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vmd_create_new_bus(struct vmd_pci_bus *parent, struct vmd_pci_device *bridge, uint8_t bus_number)
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{
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vmd_pci_bus *new_bus;
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struct vmd_pci_bus *new_bus;
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new_bus = (vmd_pci_bus *)calloc(1, sizeof(vmd_pci_bus));
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new_bus = calloc(1, sizeof(*new_bus));
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if (!new_bus) {
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return NULL;
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}
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@ -465,12 +475,13 @@ vmd_create_new_bus(vmd_pci_bus *parent, vmd_pci_device *bridge, uint8_t bus_numb
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* assign the next bus number from the vmd bus number list.
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*/
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static uint8_t
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vmd_get_next_bus_number(vmd_pci_device *dev, vmd_adapter *vmd)
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vmd_get_next_bus_number(struct vmd_pci_device *dev, struct vmd_adapter *vmd)
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{
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uint8_t bus = 0xff;
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struct vmd_pci_bus *hp_bus;
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if (dev) {
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vmd_pci_bus *hp_bus = vmd_is_dev_in_hotplug_path(dev);
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hp_bus = vmd_is_dev_in_hotplug_path(dev);
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if (hp_bus && hp_bus->self && hp_bus->self->hp) {
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return vmd_hp_get_next_bus_number(hp_bus->self->hp);
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}
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@ -485,7 +496,7 @@ vmd_get_next_bus_number(vmd_pci_device *dev, vmd_adapter *vmd)
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}
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static uint8_t
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vmd_get_hotplug_bus_numbers(vmd_pci_device *dev)
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vmd_get_hotplug_bus_numbers(struct vmd_pci_device *dev)
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{
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uint8_t bus_number = 0xff;
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@ -499,7 +510,7 @@ vmd_get_hotplug_bus_numbers(vmd_pci_device *dev)
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}
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static void
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vmd_enable_msix(vmd_pci_device *dev)
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vmd_enable_msix(struct vmd_pci_device *dev)
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{
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volatile uint16_t control;
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@ -514,7 +525,7 @@ vmd_enable_msix(vmd_pci_device *dev)
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}
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static void
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vmd_disable_msix(vmd_pci_device *dev)
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vmd_disable_msix(struct vmd_pci_device *dev)
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{
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volatile uint16_t control;
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@ -530,7 +541,7 @@ vmd_disable_msix(vmd_pci_device *dev)
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* port interrupt, so vector 0 is mapped to all MSIX entries for the port.
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*/
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static void
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vmd_setup_msix(vmd_pci_device *dev, volatile struct _pci_misx_table_entry *vmdEntry)
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vmd_setup_msix(struct vmd_pci_device *dev, volatile struct pci_msix_table_entry *vmdEntry)
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{
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int entry;
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@ -550,10 +561,10 @@ vmd_setup_msix(vmd_pci_device *dev, volatile struct _pci_misx_table_entry *vmdEn
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}
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static void
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vmd_bus_update_bridge_info(vmd_pci_device *bridge)
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vmd_bus_update_bridge_info(struct vmd_pci_device *bridge)
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{
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/* Update the subordinate bus of all bridges above this bridge */
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volatile vmd_pci_device *dev = bridge;
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volatile struct vmd_pci_device *dev = bridge;
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uint8_t subordinate_bus;
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if (!dev) {
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@ -570,13 +581,13 @@ vmd_bus_update_bridge_info(vmd_pci_device *bridge)
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}
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static bool
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vmd_is_supported_device(vmd_pci_device *dev)
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vmd_is_supported_device(struct vmd_pci_device *dev)
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{
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return dev->class == PCI_CLASS_STORAGE_EXPRESS;
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}
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static void
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vmd_dev_init(vmd_pci_device *dev)
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vmd_dev_init(struct vmd_pci_device *dev)
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{
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uint8_t bdf[32];
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@ -608,13 +619,14 @@ vmd_dev_init(vmd_pci_device *dev)
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* Return count of how many devices found(type1 + type 0 header devices)
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*/
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static uint8_t
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vmd_scan_single_bus(vmd_pci_bus *bus, vmd_pci_device *parent_bridge)
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vmd_scan_single_bus(struct vmd_pci_bus *bus, struct vmd_pci_device *parent_bridge)
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{
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/* assuming only single function devices are on the bus */
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vmd_pci_device *new_dev;
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vmd_pci_bus *new_bus;
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int device_number, dev_cnt = 0;
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express_slot_capabiliies_register slot_cap;
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struct vmd_pci_device *new_dev;
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struct vmd_adapter *vmd;
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union express_slot_capabilities_register slot_cap;
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struct vmd_pci_bus *new_bus;
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uint8_t device_number, dev_cnt = 0;
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uint8_t new_bus_num;
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for (device_number = 0; device_number < 32; device_number++) {
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@ -677,7 +689,7 @@ vmd_scan_single_bus(vmd_pci_bus *bus, vmd_pci_device *parent_bridge)
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vmd_setup_msix(new_dev, &bus->vmd->msix_table[0]);
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vmd_dev_init(new_dev);
|
||||
if (vmd_is_supported_device(new_dev)) {
|
||||
vmd_adapter *vmd = bus->vmd;
|
||||
vmd = bus->vmd;
|
||||
vmd->target[vmd->nvme_count] = new_dev;
|
||||
vmd->nvme_count++;
|
||||
}
|
||||
@ -695,7 +707,7 @@ vmd_scan_single_bus(vmd_pci_bus *bus, vmd_pci_device *parent_bridge)
|
||||
}
|
||||
|
||||
static void
|
||||
vmd_print_pci_info(vmd_pci_device *dev)
|
||||
vmd_print_pci_info(struct vmd_pci_device *dev)
|
||||
{
|
||||
if (!dev) {
|
||||
return;
|
||||
@ -740,9 +752,10 @@ vmd_print_pci_info(vmd_pci_device *dev)
|
||||
}
|
||||
|
||||
static void
|
||||
vmd_pci_print(vmd_pci_bus *bus_list)
|
||||
vmd_pci_print(struct vmd_pci_bus *bus_list)
|
||||
{
|
||||
vmd_pci_bus *bus = bus_list;
|
||||
struct vmd_pci_bus *bus = bus_list;
|
||||
struct vmd_pci_device *dev;
|
||||
|
||||
SPDK_INFOLOG(SPDK_LOG_VMD, "\n ...PCIE devices attached to VMD %04x:%02x:%02x:%x...\n",
|
||||
bus_list->vmd->pci.addr.domain, bus_list->vmd->pci.addr.bus,
|
||||
@ -751,7 +764,7 @@ vmd_pci_print(vmd_pci_bus *bus_list)
|
||||
|
||||
while (bus != NULL) {
|
||||
vmd_print_pci_info(bus->self);
|
||||
vmd_pci_device *dev = bus->dev_list;
|
||||
dev = bus->dev_list;
|
||||
while (dev != NULL) {
|
||||
vmd_print_pci_info(dev);
|
||||
dev = dev->next;
|
||||
@ -761,27 +774,26 @@ vmd_pci_print(vmd_pci_bus *bus_list)
|
||||
}
|
||||
|
||||
static uint8_t
|
||||
vmd_scan_pcibus(vmd_pci_bus *bus)
|
||||
vmd_scan_pcibus(struct vmd_pci_bus *bus)
|
||||
{
|
||||
vmd_pci_bus *new_bus = bus;
|
||||
int dev_cnt;
|
||||
uint8_t dev_cnt;
|
||||
|
||||
g_end_device_count = 0;
|
||||
vmd_add_bus_to_list(bus->vmd, new_bus);
|
||||
vmd_add_bus_to_list(bus->vmd, bus);
|
||||
bus->vmd->next_bus_number = bus->bus_number + 1;
|
||||
dev_cnt = vmd_scan_single_bus(new_bus, NULL);
|
||||
dev_cnt = vmd_scan_single_bus(bus, NULL);
|
||||
|
||||
SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %d devices\n", dev_cnt);
|
||||
SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %d END DEVICES\n", g_end_device_count);
|
||||
SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %u devices\n", dev_cnt);
|
||||
SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %u END DEVICES\n", g_end_device_count);
|
||||
|
||||
vmd_pci_print(bus->vmd->bus_list);
|
||||
|
||||
return (uint8_t)dev_cnt;
|
||||
return dev_cnt;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
vmd_map_bars(vmd_adapter *vmd, struct spdk_pci_device *dev)
|
||||
vmd_map_bars(struct vmd_adapter *vmd, struct spdk_pci_device *dev)
|
||||
{
|
||||
int rc = spdk_pci_device_map_bar(dev, 0, (void **)&vmd->cfg_vaddr,
|
||||
&vmd->cfgbar, &vmd->cfgbar_size);
|
||||
@ -803,7 +815,7 @@ vmd_map_bars(vmd_adapter *vmd, struct spdk_pci_device *dev)
|
||||
}
|
||||
|
||||
static int
|
||||
vmd_enumerate_devices(vmd_adapter *vmd)
|
||||
vmd_enumerate_devices(struct vmd_adapter *vmd)
|
||||
{
|
||||
vmd->vmd_bus.vmd = vmd;
|
||||
vmd->vmd_bus.secondary_bus = vmd->vmd_bus.subordinate_bus = 0;
|
||||
@ -868,6 +880,8 @@ int
|
||||
spdk_vmd_pci_device_list(struct spdk_pci_addr vmd_addr, struct spdk_pci_device *nvme_list)
|
||||
{
|
||||
int cnt = 0;
|
||||
struct vmd_pci_bus *bus;
|
||||
struct vmd_pci_device *dev;
|
||||
|
||||
if (!nvme_list) {
|
||||
return -1;
|
||||
@ -875,9 +889,9 @@ spdk_vmd_pci_device_list(struct spdk_pci_addr vmd_addr, struct spdk_pci_device *
|
||||
|
||||
for (int i = 0; i < MAX_VMD_TARGET; ++i) {
|
||||
if (spdk_pci_addr_compare(&vmd_addr, &g_vmd_container.vmd[i].pci.addr) == 0) {
|
||||
vmd_pci_bus *bus = g_vmd_container.vmd[i].bus_list;
|
||||
bus = g_vmd_container.vmd[i].bus_list;
|
||||
while (bus != NULL) {
|
||||
vmd_pci_device *dev = bus->dev_list;
|
||||
dev = bus->dev_list;
|
||||
while (dev != NULL) {
|
||||
nvme_list[cnt++] = dev->pci;
|
||||
if (!dev->is_hooked) {
|
||||
|
||||
@ -45,7 +45,13 @@ struct vmd_hot_plug;
|
||||
struct vmd_adapter;
|
||||
struct vmd_pci_device;
|
||||
|
||||
typedef struct vmd_pci_bus {
|
||||
struct pci_bars {
|
||||
uint64_t vaddr;
|
||||
uint64_t start;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
struct vmd_pci_bus {
|
||||
struct vmd_adapter *vmd;
|
||||
struct vmd_pci_bus *parent; /* parent bus that this bus is attached to(primary bus. */
|
||||
struct vmd_pci_device *self; /* Pci device that describes this bus(bar, bus numbers, etc */
|
||||
@ -63,22 +69,22 @@ typedef struct vmd_pci_bus {
|
||||
|
||||
struct vmd_pci_device *dev_list; /* list of pci end device attached to this bus */
|
||||
struct vmd_pci_bus *next; /* link for all buses found during scan */
|
||||
} vmd_pci_bus;
|
||||
};
|
||||
|
||||
typedef struct vmd_pci_device {
|
||||
struct vmd_pci_device {
|
||||
struct spdk_pci_device pci;
|
||||
struct pci_bars bar[6];
|
||||
|
||||
struct vmd_pci_device *parent_bridge, *next;
|
||||
vmd_pci_bus *bus, *parent;
|
||||
vmd_pci_bus *bus_object; /* bus tracks pci bus associated with this dev if type 1 dev. */
|
||||
vmd_pci_bus *subordinate;
|
||||
volatile pci_header *header;
|
||||
volatile pci_express_cap *pcie_cap;
|
||||
volatile pci_msix_capability *msix_cap;
|
||||
volatile pci_msi_cap *msi_cap;
|
||||
volatile serial_number_capability *sn_cap;
|
||||
volatile pci_msix_table_entry *msix_table;
|
||||
struct vmd_pci_bus *bus, *parent;
|
||||
struct vmd_pci_bus *bus_object; /* bus tracks pci bus associated with this dev if type 1 dev. */
|
||||
struct vmd_pci_bus *subordinate;
|
||||
volatile struct pci_header *header;
|
||||
volatile struct pci_express_cap *pcie_cap;
|
||||
volatile struct pci_msix_capability *msix_cap;
|
||||
volatile struct pci_msi_cap *msi_cap;
|
||||
volatile struct serial_number_capability *sn_cap;
|
||||
volatile struct pci_msix_table_entry *msix_table;
|
||||
|
||||
uint32_t class;
|
||||
uint16_t vid;
|
||||
@ -95,7 +101,7 @@ typedef struct vmd_pci_device {
|
||||
uint32_t target : 16;
|
||||
|
||||
struct vmd_hot_plug *hp;
|
||||
} vmd_pci_device;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
@ -108,23 +114,23 @@ struct pci_mem_mgr {
|
||||
uint64_t addr;
|
||||
};
|
||||
|
||||
typedef struct vmd_hot_plug {
|
||||
struct vmd_hot_plug {
|
||||
uint32_t count : 12;
|
||||
uint32_t reserved_bus_count : 4;
|
||||
uint32_t max_hotplug_bus_number : 8;
|
||||
uint32_t next_bus_number : 8;
|
||||
uint32_t addr_size;
|
||||
uint64_t physical_addr;
|
||||
express_slot_status_register slot_status;
|
||||
union express_slot_status_register slot_status;
|
||||
struct pci_mem_mgr mem[ADDR_ELEM_COUNT];
|
||||
uint8_t bus_numbers[RESERVED_HOTPLUG_BUSES];
|
||||
vmd_pci_bus *bus;
|
||||
} vmd_hot_plug;
|
||||
struct vmd_pci_bus *bus;
|
||||
};
|
||||
|
||||
/*
|
||||
* The VMD adapter
|
||||
*/
|
||||
typedef struct vmd_adapter {
|
||||
struct vmd_adapter {
|
||||
struct spdk_pci_device pci;
|
||||
uint32_t domain;
|
||||
/* physical and virtual VMD bars */
|
||||
@ -134,7 +140,7 @@ typedef struct vmd_adapter {
|
||||
volatile uint8_t *cfg_vaddr;
|
||||
volatile uint8_t *mem_vaddr;
|
||||
volatile uint8_t *msix_vaddr;
|
||||
volatile struct _pci_misx_table_entry *msix_table;
|
||||
volatile struct pci_msix_table_entry *msix_table;
|
||||
uint32_t bar_sizes[6];
|
||||
|
||||
uint64_t physical_addr;
|
||||
@ -157,12 +163,11 @@ typedef struct vmd_adapter {
|
||||
struct vmd_pci_bus vmd_bus, *bus_list;
|
||||
|
||||
struct event_fifo *hp_queue;
|
||||
|
||||
} vmd_adapter;
|
||||
};
|
||||
|
||||
/* TODO: Temporary stubs for Hot Plug interface */
|
||||
static inline vmd_pci_bus *
|
||||
vmd_is_dev_in_hotplug_path(vmd_pci_device *dev)
|
||||
static inline struct vmd_pci_bus *
|
||||
vmd_is_dev_in_hotplug_path(struct vmd_pci_device *dev)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
@ -181,7 +186,7 @@ vmd_hp_enable_hotplug(struct vmd_hot_plug *hp)
|
||||
}
|
||||
|
||||
static inline struct vmd_hot_plug *
|
||||
vmd_new_hotplug(vmd_pci_bus *newBus, uint8_t reservedBuses)
|
||||
vmd_new_hotplug(struct vmd_pci_bus *newBus, uint8_t reservedBuses)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -116,19 +116,19 @@
|
||||
|
||||
#define BAR_SIZE (1 << 20)
|
||||
|
||||
typedef struct _enhanced_capability_hdr {
|
||||
struct pci_enhanced_capability_header {
|
||||
uint16_t capability_id;
|
||||
uint16_t version: 4;
|
||||
uint16_t next: 12;
|
||||
} pci_enhanced_capability_header;
|
||||
};
|
||||
|
||||
typedef struct _SerialNumberCapability {
|
||||
pci_enhanced_capability_header hdr;
|
||||
struct serial_number_capability {
|
||||
struct pci_enhanced_capability_header hdr;
|
||||
uint32_t sn_low;
|
||||
uint32_t sn_hi;
|
||||
} serial_number_capability;
|
||||
};
|
||||
|
||||
typedef struct _PciHeaderCommon {
|
||||
struct pci_header_common {
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint16_t command;
|
||||
@ -144,9 +144,9 @@ typedef struct _PciHeaderCommon {
|
||||
uint8_t int_line;
|
||||
uint8_t int_pin;
|
||||
uint8_t rsvd62[2];
|
||||
} pci_header_common;
|
||||
};
|
||||
|
||||
typedef struct _PciTypeZeroHeader {
|
||||
struct pci_header_zero {
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint16_t command;
|
||||
@ -167,9 +167,9 @@ typedef struct _PciTypeZeroHeader {
|
||||
uint8_t int_pin;
|
||||
uint8_t min_gnt;
|
||||
uint8_t max_lat;
|
||||
} pci_header_zero;
|
||||
};
|
||||
|
||||
typedef struct _PciTypeOneHeader {
|
||||
struct pci_header_one {
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint16_t command;
|
||||
@ -201,13 +201,12 @@ typedef struct _PciTypeOneHeader {
|
||||
uint8_t int_line;
|
||||
uint8_t int_pin;
|
||||
uint16_t bridge_control;
|
||||
} pci_header_one;
|
||||
};
|
||||
|
||||
|
||||
typedef struct _PciCapHdr {
|
||||
struct pci_capabilities_header {
|
||||
uint8_t capability_id;
|
||||
uint8_t next;
|
||||
} pci_capabilities_header;
|
||||
};
|
||||
|
||||
/*
|
||||
* MSI capability structure for msi interrupt vectors
|
||||
@ -216,8 +215,8 @@ typedef struct _PciCapHdr {
|
||||
#define MSIX_ENTRY_VECTOR_CTRL_MASKBIT 1
|
||||
#define PORT_INT_VECTOR 0;
|
||||
#define CLEAR_MSIX_DESTINATION_ID 0xfff00fff
|
||||
struct PCI_MSI_CAPABILITY {
|
||||
pci_capabilities_header header;
|
||||
struct pci_msi_cap {
|
||||
struct pci_capabilities_header header;
|
||||
union _MsiControl {
|
||||
uint16_t as_uint16_t;
|
||||
struct _PCI_MSI_MESSAGE_CONTROL {
|
||||
@ -249,9 +248,8 @@ struct PCI_MSI_CAPABILITY {
|
||||
} option64_bit;
|
||||
};
|
||||
};
|
||||
typedef struct PCI_MSI_CAPABILITY pci_msi_cap;
|
||||
|
||||
typedef struct PcixTablePointer {
|
||||
struct pcix_table_pointer {
|
||||
union {
|
||||
struct {
|
||||
uint32_t BaseIndexRegister : 3;
|
||||
@ -259,10 +257,10 @@ typedef struct PcixTablePointer {
|
||||
} TableBIR;
|
||||
uint32_t TableOffset;
|
||||
};
|
||||
} pcix_table_pointer;
|
||||
};
|
||||
|
||||
typedef struct _PciMsixCapability {
|
||||
struct _PciCapHdr header;
|
||||
struct pci_msix_capability {
|
||||
struct pci_capabilities_header header;
|
||||
union _MsixControl {
|
||||
uint16_t as_uint16_t;
|
||||
struct msg_ctrl {
|
||||
@ -273,34 +271,43 @@ typedef struct _PciMsixCapability {
|
||||
} bit;
|
||||
} message_control;
|
||||
|
||||
pcix_table_pointer message_table;
|
||||
pcix_table_pointer pba_table;
|
||||
} pci_msix_capability;
|
||||
struct pcix_table_pointer message_table;
|
||||
struct pcix_table_pointer pba_table;
|
||||
};
|
||||
|
||||
typedef struct _pci_misx_table_entry {
|
||||
struct pci_msix_table_entry {
|
||||
volatile uint32_t message_addr_lo;
|
||||
volatile uint32_t message_addr_hi;
|
||||
volatile uint32_t message_data;
|
||||
volatile uint32_t vector_control;
|
||||
} pci_msix_table_entry;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pci express capability
|
||||
*/
|
||||
enum PciExpressCapabilities {
|
||||
LegacyEndpoint = 0x1, /* 0001b Legacy PCI Express Endpoint */
|
||||
ExpressEndpoint = 0x0, /* 0000b PCI Express Endpoint */
|
||||
RootComplexRootPort = 0x4, /* 0100b Root Port of PCI Express Root Complex* */
|
||||
SwitchUpstreamPort = 0x5, /* 0101b Upstream Port of PCI Express Switch* */
|
||||
SwitchDownStreamPort = 0x6, /* 0110b Downstream Port of PCI Express Switch* */
|
||||
ExpressToPciBridge = 0x7, /* 0111b PCI Express to PCI/PCI-X Bridge* */
|
||||
PciToExpressBridge = 0x8, /* 1000b PCI/PCI-X to PCI Express Bridge* */
|
||||
RCIntegratedEndpoint = 0x9, /* 1001b Root Complex Integrated Endpoint */
|
||||
RootComplexEventCollector = 0xa, /* 1010b Root Complex Event Collector */
|
||||
/* 0001b Legacy PCI Express Endpoint */
|
||||
LegacyEndpoint = 0x1,
|
||||
/* 0000b PCI Express Endpoint */
|
||||
ExpressEndpoint = 0x0,
|
||||
/* 0100b Root Port of PCI Express Root Complex* */
|
||||
RootComplexRootPort = 0x4,
|
||||
/* 0101b Upstream Port of PCI Express Switch* */
|
||||
SwitchUpstreamPort = 0x5,
|
||||
/* 0110b Downstream Port of PCI Express Switch* */
|
||||
SwitchDownStreamPort = 0x6,
|
||||
/* 0111b PCI Express to PCI/PCI-X Bridge* */
|
||||
ExpressToPciBridge = 0x7,
|
||||
/* 1000b PCI/PCI-X to PCI Express Bridge* */
|
||||
PciToExpressBridge = 0x8,
|
||||
/* 1001b Root Complex Integrated Endpoint */
|
||||
RCIntegratedEndpoint = 0x9,
|
||||
/* 1010b Root Complex Event Collector */
|
||||
RootComplexEventCollector = 0xa,
|
||||
InvalidCapability = 0xff
|
||||
};
|
||||
|
||||
typedef union _EXPRESS_CAPABILITIES_REGISTER {
|
||||
union express_capability_register {
|
||||
struct {
|
||||
uint16_t capability_version : 4;
|
||||
uint16_t device_type : 4;
|
||||
@ -309,116 +316,9 @@ typedef union _EXPRESS_CAPABILITIES_REGISTER {
|
||||
uint16_t rsv : 2;
|
||||
} bit_field;
|
||||
uint16_t as_uint16_t;
|
||||
} express_capability_register;
|
||||
};
|
||||
|
||||
typedef union _EXPRESS_DEVICE_CAPABILITIES_REGISTER {
|
||||
struct {
|
||||
uint32_t max_payload_size_supported : 3;
|
||||
uint32_t phantom_functions_supported : 2;
|
||||
uint32_t extended_tag_supported : 1;
|
||||
uint32_t L0s_acceptable_latency : 3;
|
||||
uint32_t L1_acceptable_latency : 3;
|
||||
uint32_t undefined : 3;
|
||||
uint32_t role_based_error_reporting : 1;
|
||||
uint32_t rsvd1 : 2;
|
||||
uint32_t captured_slot_power_limit : 8;
|
||||
uint32_t captured_slot_power_limit_scale : 2;
|
||||
uint32_t rsvd2 : 4;
|
||||
} bit_field;
|
||||
uint32_t as_uint32_t;
|
||||
} express_device_capability_register;
|
||||
|
||||
/*
|
||||
* The low 3 bits of the PCI Express device control register dictate whether
|
||||
* a device that implements AER routes error messages to the root complex.
|
||||
* This mask is used when programming the AER bits in the device control
|
||||
* register.
|
||||
*/
|
||||
#define EXPRESS_AER_DEVICE_CONTROL_MASK 0x07;
|
||||
typedef union _EXPRESS_DEVICE_CONTROL_REGISTER {
|
||||
struct {
|
||||
uint16_t correctable_error_enable : 1;
|
||||
uint16_t non_fatal_error_enable : 1;
|
||||
uint16_t fatal_error_enable : 1;
|
||||
uint16_t unsupported_request_error_enable : 1;
|
||||
uint16_t enable_relaxed_order : 1;
|
||||
uint16_t max_payload_size : 3;
|
||||
uint16_t extended_tag_enable : 1;
|
||||
uint16_t phantom_functions_enable : 1;
|
||||
uint16_t aux_power_enable : 1;
|
||||
uint16_t no_snoop_enable : 1;
|
||||
uint16_t max_read_request_size : 3;
|
||||
uint16_t bridge_config_retry_enable : 1;
|
||||
} bit_field;
|
||||
uint16_t as_uint16_t;;
|
||||
} express_device_control_register;
|
||||
|
||||
/*
|
||||
* The low 4 bits of the PCI Express device status register hold AER device
|
||||
* status. This mask is used when programming the AER bits in the device status
|
||||
* register.
|
||||
*/
|
||||
#define EXPRESS_AER_DEVICE_STATUS_MASK 0x0F;
|
||||
typedef union _EXPRESS_DEVICE_STATUS_REGISTER {
|
||||
struct {
|
||||
uint16_t CorrectableErrorDetected : 1;
|
||||
uint16_t NonFatalErrorDetected : 1;
|
||||
uint16_t FatalErrorDetected : 1;
|
||||
uint16_t UnsupportedRequestDetected : 1;
|
||||
uint16_t AuxPowerDetected : 1;
|
||||
uint16_t TransactionsPending : 1;
|
||||
uint16_t Rsvd : 10;
|
||||
} bit_field;
|
||||
uint16_t Asuint16_t;
|
||||
} express_device_status_register;
|
||||
|
||||
typedef union _EXPRESS_LINK_CAPABILITIES_REGISTER {
|
||||
struct {
|
||||
uint32_t MaximumLinkSpeed : 4;
|
||||
uint32_t MaximumLinkWidth : 6;
|
||||
uint32_t ActiveStatePMSupport : 2;
|
||||
uint32_t L0sExitLatency : 3;
|
||||
uint32_t L1ExitLatency : 3;
|
||||
uint32_t ClockPowerManagement : 1;
|
||||
uint32_t SurpriseDownErrorReportingCapable : 1;
|
||||
uint32_t DataLinkLayerActiveReportingCapable : 1;
|
||||
uint32_t LinkBandwidthNotificationCapability : 1;
|
||||
uint32_t AspmOptionalityCompliance : 1;
|
||||
uint32_t Rsvd : 1;
|
||||
uint32_t PortNumber : 8;
|
||||
} bit_field;
|
||||
uint32_t Asuint32_t;
|
||||
} express_link_capability_register;
|
||||
|
||||
typedef union _EXPRESS_LINK_CONTROL_REGISTER {
|
||||
struct {
|
||||
uint16_t ActiveStatePMControl : 2;
|
||||
uint16_t Rsvd1 : 1;
|
||||
uint16_t ReadCompletionBoundary : 1;
|
||||
uint16_t LinkDisable : 1;
|
||||
uint16_t RetrainLink : 1;
|
||||
uint16_t CommonClockConfig : 1;
|
||||
uint16_t ExtendedSynch : 1;
|
||||
uint16_t EnableClockPowerManagement : 1;
|
||||
uint16_t Rsvd2 : 7;
|
||||
} bit_field;
|
||||
uint16_t Asuint16_t;
|
||||
} express_link_control_register;
|
||||
|
||||
typedef union _EXPRESS_LINK_STATUS_REGISTER {
|
||||
struct {
|
||||
uint16_t LinkSpeed : 4;
|
||||
uint16_t LinkWidth : 6;
|
||||
uint16_t Undefined : 1;
|
||||
uint16_t LinkTraining : 1;
|
||||
uint16_t SlotClockConfig : 1;
|
||||
uint16_t DataLinkLayerActive : 1;
|
||||
uint16_t Rsvd : 2;
|
||||
} bitField;
|
||||
uint16_t Asuint16_t;
|
||||
} express_link_status_register;
|
||||
|
||||
typedef union _EXPRESS_SLOT_CAPABILITIES_REGISTER {
|
||||
union express_slot_capabilities_register {
|
||||
struct {
|
||||
uint32_t attention_button_present : 1;
|
||||
uint32_t power_controller_present : 1;
|
||||
@ -434,9 +334,9 @@ typedef union _EXPRESS_SLOT_CAPABILITIES_REGISTER {
|
||||
uint32_t physical_slot_number : 13;
|
||||
} bit_field;
|
||||
uint32_t as_uint32_t;
|
||||
} express_slot_capabiliies_register;
|
||||
};
|
||||
|
||||
typedef union _EXPRESS_SLOT_CONTROL_REGISTER {
|
||||
union express_slot_control_register {
|
||||
struct {
|
||||
uint16_t attention_button_enable : 1;
|
||||
uint16_t power_fault_detect_enable : 1;
|
||||
@ -452,9 +352,9 @@ typedef union _EXPRESS_SLOT_CONTROL_REGISTER {
|
||||
uint16_t Rsvd : 3;
|
||||
} bit_field;
|
||||
uint16_t as_uint16_t;
|
||||
} express_slot_control_register;
|
||||
};
|
||||
|
||||
typedef union _EXPRESS_SLOT_STATUS_REGISTER {
|
||||
union express_slot_status_register {
|
||||
struct {
|
||||
uint16_t attention_button_pressed : 1;
|
||||
uint16_t power_fault_detected : 1;
|
||||
@ -468,9 +368,9 @@ typedef union _EXPRESS_SLOT_STATUS_REGISTER {
|
||||
uint16_t rsvd : 7;
|
||||
} bit_field;
|
||||
uint16_t as_uint16_t;
|
||||
} express_slot_status_register;
|
||||
};
|
||||
|
||||
typedef union _EXPRESS_ROOT_CONTROL_REGISTER {
|
||||
union express_root_control_register {
|
||||
struct {
|
||||
uint16_t CorrectableSerrEnable : 1;
|
||||
uint16_t NonFatalSerrEnable : 1;
|
||||
@ -482,20 +382,19 @@ typedef union _EXPRESS_ROOT_CONTROL_REGISTER {
|
||||
uint16_t as_uint16_t;
|
||||
} express_root_control_register;
|
||||
|
||||
|
||||
typedef struct _PciExpressCap {
|
||||
struct pci_express_cap {
|
||||
uint8_t capid;
|
||||
uint8_t next_cap;
|
||||
express_capability_register express_cap_register;
|
||||
union express_capability_register express_cap_register;
|
||||
uint32_t device_cap;
|
||||
uint16_t device_control;
|
||||
uint16_t device_status;
|
||||
uint32_t link_cap;
|
||||
uint16_t link_control;
|
||||
uint16_t link_status;
|
||||
express_slot_capabiliies_register slot_cap;
|
||||
express_slot_control_register slot_control;
|
||||
express_slot_status_register slot_status;
|
||||
union express_slot_capabilities_register slot_cap;
|
||||
union express_slot_control_register slot_control;
|
||||
union express_slot_status_register slot_status;
|
||||
uint32_t root_status;
|
||||
uint32_t deviceCap2;
|
||||
uint16_t deviceControl2;
|
||||
@ -506,28 +405,22 @@ typedef struct _PciExpressCap {
|
||||
uint32_t slotCap2;
|
||||
uint16_t slotControl2;
|
||||
uint16_t slotStatus2;
|
||||
} pci_express_cap;
|
||||
};
|
||||
|
||||
typedef struct _PciMsixCap {
|
||||
struct pci_msix_cap {
|
||||
uint8_t cap_idd;
|
||||
uint8_t next_cap;
|
||||
uint16_t msg_control_reg;
|
||||
uint32_t msix_table_offset;
|
||||
uint32_t pba_offset;
|
||||
} pci_msix_cap;
|
||||
};
|
||||
|
||||
typedef struct _PciHeader {
|
||||
struct pci_header {
|
||||
union {
|
||||
pci_header_common common;
|
||||
pci_header_zero zero;
|
||||
pci_header_one one;
|
||||
struct pci_header_common common;
|
||||
struct pci_header_zero zero;
|
||||
struct pci_header_one one;
|
||||
};
|
||||
} pci_header;
|
||||
|
||||
struct pci_bars {
|
||||
uint64_t vaddr;
|
||||
uint64_t start;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
#endif /* VMD_SPEC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user