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lib/vmd: Removed typedefs from structures definitions

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Removed typedefs and unused structures.

Change-Id: I711094097520333cbeda2f26a1a7d403750070b1
Signed-off-by: Wojciech Malikowski <wojciech.malikowski@intel.com>
Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/456479
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
This commit is contained in:
Wojciech Malikowski 2019-05-31 08:51:52 -04:00 committed by Jim Harris
parent f7e68be171
commit d3a0531bc1
3 changed files with 216 additions and 304 deletions
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190
lib/vmd/vmd.c
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@ -57,21 +57,21 @@ struct vmd_container {
uint32_t count; uint32_t count;
/* can target specific vmd or all vmd when null */ /* can target specific vmd or all vmd when null */
struct spdk_pci_addr *vmd_target_addr; struct spdk_pci_addr *vmd_target_addr;
vmd_adapter vmd[MAX_VMD_SUPPORTED]; struct vmd_adapter vmd[MAX_VMD_SUPPORTED];
}; };
static struct vmd_container g_vmd_container; static struct vmd_container g_vmd_container;
static int g_end_device_count; static uint8_t g_end_device_count;
static bool static bool
vmd_is_valid_cfg_addr(vmd_pci_bus *bus, uint64_t addr) vmd_is_valid_cfg_addr(struct vmd_pci_bus *bus, uint64_t addr)
{ {
return addr >= (uint64_t)bus->vmd->cfg_vaddr && return addr >= (uint64_t)bus->vmd->cfg_vaddr &&
addr < bus->vmd->cfgbar_size + (uint64_t)bus->vmd->cfg_vaddr; addr < bus->vmd->cfgbar_size + (uint64_t)bus->vmd->cfg_vaddr;
} }
static void static void
vmd_align_base_addrs(vmd_adapter *vmd, uint32_t alignment) vmd_align_base_addrs(struct vmd_adapter *vmd, uint32_t alignment)
{ {
uint32_t pad; uint32_t pad;
/* /*
@ -94,9 +94,10 @@ vmd_align_base_addrs(vmd_adapter *vmd, uint32_t alignment)
* Consider increasing the size of vmd membar if 0x0 is returned. * Consider increasing the size of vmd membar if 0x0 is returned.
*/ */
static uint64_t static uint64_t
vmd_allocate_base_addr(vmd_adapter *vmd, vmd_pci_device *dev, uint32_t size) vmd_allocate_base_addr(struct vmd_adapter *vmd, struct vmd_pci_device *dev, uint32_t size)
{ {
uint64_t base_address = 0; uint64_t base_address = 0;
struct vmd_pci_bus *hp_bus;
if (size && ((size & (~size + 1)) != size)) { if (size && ((size & (~size + 1)) != size)) {
return base_address; return base_address;
@ -109,7 +110,7 @@ vmd_allocate_base_addr(vmd_adapter *vmd, vmd_pci_device *dev, uint32_t size)
* get a buffer from the unused chunk. First fit algorithm, is used. * get a buffer from the unused chunk. First fit algorithm, is used.
*/ */
if (dev) { if (dev) {
vmd_pci_bus *hp_bus = vmd_is_dev_in_hotplug_path(dev); hp_bus = vmd_is_dev_in_hotplug_path(dev);
if (hp_bus && hp_bus->self) { if (hp_bus && hp_bus->self) {
return vmd_hp_allocate_base_addr(hp_bus->self->hp, size); return vmd_hp_allocate_base_addr(hp_bus->self->hp, size);
} }
@ -135,44 +136,50 @@ vmd_allocate_base_addr(vmd_adapter *vmd, vmd_pci_device *dev, uint32_t size)
} }
static bool static bool
vmd_is_end_device(vmd_pci_device *dev) vmd_is_end_device(struct vmd_pci_device *dev)
{ {
return (dev && dev->header) && return (dev && dev->header) &&
((dev->header->common.header_type & ~PCI_MULTI_FUNCTION) == PCI_HEADER_TYPE_NORMAL); ((dev->header->common.header_type & ~PCI_MULTI_FUNCTION) == PCI_HEADER_TYPE_NORMAL);
} }
static void static void
vmd_update_base_limit_register(vmd_pci_device *dev, uint16_t base, uint16_t limit) vmd_update_base_limit_register(struct vmd_pci_device *dev, uint16_t base, uint16_t limit)
{ {
if (base && limit && dev != NULL) { struct vmd_pci_bus *bus = dev->parent;
vmd_pci_bus *bus = dev->parent; struct vmd_pci_device *bridge;
while (bus && bus->self != NULL) {
vmd_pci_device *bridge = bus->self;
/* This is only for 32-bit memory space, need to revisit to support 64-bit */ if (base == 0 || limit == 0) {
if (bridge->header->one.mem_base > base) { return;
bridge->header->one.mem_base = base; }
base = bridge->header->one.mem_base;
}
if (bridge->header->one.mem_limit < limit) { while (bus && bus->self != NULL) {
bridge->header->one.mem_limit = limit; bridge = bus->self;
limit = bridge->header->one.mem_limit;
} /* This is only for 32-bit memory space, need to revisit to support 64-bit */
bus = bus->parent; if (bridge->header->one.mem_base > base) {
bridge->header->one.mem_base = base;
base = bridge->header->one.mem_base;
} }
if (bridge->header->one.mem_limit < limit) {
bridge->header->one.mem_limit = limit;
limit = bridge->header->one.mem_limit;
}
bus = bus->parent;
} }
} }
static bool static bool
vmd_assign_base_addrs(vmd_pci_device *dev) vmd_assign_base_addrs(struct vmd_pci_device *dev)
{ {
uint16_t mem_base = 0, mem_limit = 0; uint16_t mem_base = 0, mem_limit = 0;
unsigned char mem_attr = 0; unsigned char mem_attr = 0;
int last = dev->header_type ? 2 : 6; int last = dev->header_type ? 2 : 6;
vmd_adapter *vmd = NULL; struct vmd_adapter *vmd = NULL;
bool ret_val = false; bool ret_val = false;
uint32_t bar_value; uint32_t bar_value;
uint32_t table_offset;
if (dev && dev->bus) { if (dev && dev->bus) {
vmd = dev->bus->vmd; vmd = dev->bus->vmd;
@ -201,7 +208,9 @@ vmd_assign_base_addrs(vmd_pci_device *dev)
dev->header->zero.BAR[i] = (uint32_t)dev->bar[i].start; dev->header->zero.BAR[i] = (uint32_t)dev->bar[i].start;
if (!dev->bar[i].start) { if (!dev->bar[i].start) {
if (mem_attr == (PCI_BAR_MEMORY_PREFETCH | PCI_BAR_MEMORY_TYPE_64)) { i++; } if (mem_attr == (PCI_BAR_MEMORY_PREFETCH | PCI_BAR_MEMORY_TYPE_64)) {
i++;
}
continue; continue;
} }
@ -228,9 +237,9 @@ vmd_assign_base_addrs(vmd_pci_device *dev)
cmd++; cmd++;
if (dev->msix_cap && ret_val) { if (dev->msix_cap && ret_val) {
uint32_t table_offset = ((volatile pci_msix_cap *)dev->msix_cap)->msix_table_offset; table_offset = ((volatile struct pci_msix_cap *)dev->msix_cap)->msix_table_offset;
if (dev->bar[table_offset & 0x3].vaddr) { if (dev->bar[table_offset & 0x3].vaddr) {
dev->msix_table = (volatile pci_msix_table_entry *) dev->msix_table = (volatile struct pci_msix_table_entry *)
(dev->bar[table_offset & 0x3].vaddr + (table_offset & 0xfff8)); (dev->bar[table_offset & 0x3].vaddr + (table_offset & 0xfff8));
} }
} }
@ -243,12 +252,12 @@ vmd_assign_base_addrs(vmd_pci_device *dev)
} }
static void static void
vmd_get_device_capabilities(vmd_pci_device *dev) vmd_get_device_capabilities(struct vmd_pci_device *dev)
{ {
volatile uint8_t *config_space; volatile uint8_t *config_space;
uint8_t capabilities_offset; uint8_t capabilities_offset;
pci_capabilities_header *capabilities_hdr; struct pci_capabilities_header *capabilities_hdr;
config_space = (volatile uint8_t *)dev->header; config_space = (volatile uint8_t *)dev->header;
if ((dev->header->common.status & PCI_CAPABILITIES_LIST) == 0) { if ((dev->header->common.status & PCI_CAPABILITIES_LIST) == 0) {
@ -261,18 +270,19 @@ vmd_get_device_capabilities(vmd_pci_device *dev)
} }
while (capabilities_offset > 0) { while (capabilities_offset > 0) {
capabilities_hdr = (pci_capabilities_header *)&config_space[capabilities_offset]; capabilities_hdr = (struct pci_capabilities_header *)
&config_space[capabilities_offset];
switch (capabilities_hdr->capability_id) { switch (capabilities_hdr->capability_id) {
case CAPABILITY_ID_PCI_EXPRESS: case CAPABILITY_ID_PCI_EXPRESS:
dev->pcie_cap = (volatile pci_express_cap *)(capabilities_hdr); dev->pcie_cap = (volatile struct pci_express_cap *)(capabilities_hdr);
break; break;
case CAPABILITY_ID_MSI: case CAPABILITY_ID_MSI:
dev->msi_cap = (volatile pci_msi_cap *)capabilities_hdr; dev->msi_cap = (volatile struct pci_msi_cap *)capabilities_hdr;
break; break;
case CAPABILITY_ID_MSIX: case CAPABILITY_ID_MSIX:
dev->msix_cap = (volatile pci_msix_capability *)capabilities_hdr; dev->msix_cap = (volatile struct pci_msix_capability *)capabilities_hdr;
dev->msix_table_size = dev->msix_cap->message_control.bit.table_size + 1; dev->msix_table_size = dev->msix_cap->message_control.bit.table_size + 1;
break; break;
@ -283,16 +293,16 @@ vmd_get_device_capabilities(vmd_pci_device *dev)
} }
} }
static volatile pci_enhanced_capability_header * static volatile struct pci_enhanced_capability_header *
vmd_get_enhanced_capabilities(vmd_pci_device *dev, uint16_t capability_id) vmd_get_enhanced_capabilities(struct vmd_pci_device *dev, uint16_t capability_id)
{ {
uint8_t *data; uint8_t *data;
uint16_t cap_offset = EXTENDED_CAPABILITY_OFFSET; uint16_t cap_offset = EXTENDED_CAPABILITY_OFFSET;
volatile pci_enhanced_capability_header *cap_hdr = NULL; volatile struct pci_enhanced_capability_header *cap_hdr = NULL;
data = (uint8_t *)dev->header; data = (uint8_t *)dev->header;
while (cap_offset >= EXTENDED_CAPABILITY_OFFSET) { while (cap_offset >= EXTENDED_CAPABILITY_OFFSET) {
cap_hdr = (volatile pci_enhanced_capability_header *) &data[cap_offset]; cap_hdr = (volatile struct pci_enhanced_capability_header *) &data[cap_offset];
if (cap_hdr->capability_id == capability_id) { if (cap_hdr->capability_id == capability_id) {
return cap_hdr; return cap_hdr;
} }
@ -306,7 +316,7 @@ vmd_get_enhanced_capabilities(vmd_pci_device *dev, uint16_t capability_id)
} }
static void static void
vmd_read_config_space(vmd_pci_device *dev) vmd_read_config_space(struct vmd_pci_device *dev)
{ {
/* /*
* Writes to the pci config space is posted weite. To ensure transaction reaches its destination * Writes to the pci config space is posted weite. To ensure transaction reaches its destination
@ -316,20 +326,20 @@ vmd_read_config_space(vmd_pci_device *dev)
{ uint16_t cmd = dev->header->common.command; (void)cmd; } { uint16_t cmd = dev->header->common.command; (void)cmd; }
vmd_get_device_capabilities(dev); vmd_get_device_capabilities(dev);
dev->sn_cap = (serial_number_capability *)vmd_get_enhanced_capabilities(dev, dev->sn_cap = (struct serial_number_capability *)vmd_get_enhanced_capabilities(dev,
DEVICE_SERIAL_NUMBER_CAP_ID); DEVICE_SERIAL_NUMBER_CAP_ID);
} }
static vmd_pci_device * static struct vmd_pci_device *
vmd_alloc_dev(vmd_pci_bus *bus, uint32_t devfn) vmd_alloc_dev(struct vmd_pci_bus *bus, uint32_t devfn)
{ {
vmd_pci_device *dev = NULL; struct vmd_pci_device *dev = NULL;
pci_header volatile *header; struct pci_header volatile *header;
uint8_t header_type; uint8_t header_type;
uint32_t rev_class; uint32_t rev_class;
header = (pci_header * volatile)(bus->vmd->cfg_vaddr + header = (struct pci_header * volatile)(bus->vmd->cfg_vaddr +
CONFIG_OFFSET_ADDR(bus->bus_number, devfn, 0, 0)); CONFIG_OFFSET_ADDR(bus->bus_number, devfn, 0, 0));
if (!vmd_is_valid_cfg_addr(bus, (uint64_t)header)) { if (!vmd_is_valid_cfg_addr(bus, (uint64_t)header)) {
return NULL; return NULL;
} }
@ -341,7 +351,7 @@ vmd_alloc_dev(vmd_pci_bus *bus, uint32_t devfn)
SPDK_DEBUGLOG(SPDK_LOG_VMD, "PCI device found: %04x:%04x ***\n", SPDK_DEBUGLOG(SPDK_LOG_VMD, "PCI device found: %04x:%04x ***\n",
header->common.vendor_id, header->common.device_id); header->common.vendor_id, header->common.device_id);
dev = calloc(1, sizeof(vmd_pci_device)); dev = calloc(1, sizeof(*dev));
if (!dev) { if (!dev) {
return NULL; return NULL;
} }
@ -375,9 +385,9 @@ vmd_alloc_dev(vmd_pci_bus *bus, uint32_t devfn)
} }
static void static void
vmd_add_bus_to_list(vmd_adapter *vmd, vmd_pci_bus *bus) vmd_add_bus_to_list(struct vmd_adapter *vmd, struct vmd_pci_bus *bus)
{ {
vmd_pci_bus *blist; struct vmd_pci_bus *blist;
blist = vmd->bus_list; blist = vmd->bus_list;
bus->next = NULL; bus->next = NULL;
@ -394,9 +404,9 @@ vmd_add_bus_to_list(vmd_adapter *vmd, vmd_pci_bus *bus)
} }
static void static void
vmd_pcibus_remove_device(vmd_pci_bus *bus, vmd_pci_device *device) vmd_pcibus_remove_device(struct vmd_pci_bus *bus, struct vmd_pci_device *device)
{ {
vmd_pci_device *list = bus->dev_list; struct vmd_pci_device *list = bus->dev_list;
if (list == device) { if (list == device) {
bus->dev_list = NULL; bus->dev_list = NULL;
@ -413,9 +423,9 @@ vmd_pcibus_remove_device(vmd_pci_bus *bus, vmd_pci_device *device)
static bool static bool
vmd_bus_add_device(vmd_pci_bus *bus, vmd_pci_device *device) vmd_bus_add_device(struct vmd_pci_bus *bus, struct vmd_pci_device *device)
{ {
vmd_pci_device *next_dev = bus->dev_list; struct vmd_pci_device *next_dev = bus->dev_list;
device->next = NULL; device->next = NULL;
if (next_dev == NULL) { if (next_dev == NULL) {
@ -432,12 +442,12 @@ vmd_bus_add_device(vmd_pci_bus *bus, vmd_pci_device *device)
return 1; return 1;
} }
static vmd_pci_bus * static struct vmd_pci_bus *
vmd_create_new_bus(vmd_pci_bus *parent, vmd_pci_device *bridge, uint8_t bus_number) vmd_create_new_bus(struct vmd_pci_bus *parent, struct vmd_pci_device *bridge, uint8_t bus_number)
{ {
vmd_pci_bus *new_bus; struct vmd_pci_bus *new_bus;
new_bus = (vmd_pci_bus *)calloc(1, sizeof(vmd_pci_bus)); new_bus = calloc(1, sizeof(*new_bus));
if (!new_bus) { if (!new_bus) {
return NULL; return NULL;
} }
@ -465,12 +475,13 @@ vmd_create_new_bus(vmd_pci_bus *parent, vmd_pci_device *bridge, uint8_t bus_numb
* assign the next bus number from the vmd bus number list. * assign the next bus number from the vmd bus number list.
*/ */
static uint8_t static uint8_t
vmd_get_next_bus_number(vmd_pci_device *dev, vmd_adapter *vmd) vmd_get_next_bus_number(struct vmd_pci_device *dev, struct vmd_adapter *vmd)
{ {
uint8_t bus = 0xff; uint8_t bus = 0xff;
struct vmd_pci_bus *hp_bus;
if (dev) { if (dev) {
vmd_pci_bus *hp_bus = vmd_is_dev_in_hotplug_path(dev); hp_bus = vmd_is_dev_in_hotplug_path(dev);
if (hp_bus && hp_bus->self && hp_bus->self->hp) { if (hp_bus && hp_bus->self && hp_bus->self->hp) {
return vmd_hp_get_next_bus_number(hp_bus->self->hp); return vmd_hp_get_next_bus_number(hp_bus->self->hp);
} }
@ -485,7 +496,7 @@ vmd_get_next_bus_number(vmd_pci_device *dev, vmd_adapter *vmd)
} }
static uint8_t static uint8_t
vmd_get_hotplug_bus_numbers(vmd_pci_device *dev) vmd_get_hotplug_bus_numbers(struct vmd_pci_device *dev)
{ {
uint8_t bus_number = 0xff; uint8_t bus_number = 0xff;
@ -499,7 +510,7 @@ vmd_get_hotplug_bus_numbers(vmd_pci_device *dev)
} }
static void static void
vmd_enable_msix(vmd_pci_device *dev) vmd_enable_msix(struct vmd_pci_device *dev)
{ {
volatile uint16_t control; volatile uint16_t control;
@ -514,7 +525,7 @@ vmd_enable_msix(vmd_pci_device *dev)
} }
static void static void
vmd_disable_msix(vmd_pci_device *dev) vmd_disable_msix(struct vmd_pci_device *dev)
{ {
volatile uint16_t control; volatile uint16_t control;
@ -530,7 +541,7 @@ vmd_disable_msix(vmd_pci_device *dev)
* port interrupt, so vector 0 is mapped to all MSIX entries for the port. * port interrupt, so vector 0 is mapped to all MSIX entries for the port.
*/ */
static void static void
vmd_setup_msix(vmd_pci_device *dev, volatile struct _pci_misx_table_entry *vmdEntry) vmd_setup_msix(struct vmd_pci_device *dev, volatile struct pci_msix_table_entry *vmdEntry)
{ {
int entry; int entry;
@ -550,10 +561,10 @@ vmd_setup_msix(vmd_pci_device *dev, volatile struct _pci_misx_table_entry *vmdEn
} }
static void static void
vmd_bus_update_bridge_info(vmd_pci_device *bridge) vmd_bus_update_bridge_info(struct vmd_pci_device *bridge)
{ {
/* Update the subordinate bus of all bridges above this bridge */ /* Update the subordinate bus of all bridges above this bridge */
volatile vmd_pci_device *dev = bridge; volatile struct vmd_pci_device *dev = bridge;
uint8_t subordinate_bus; uint8_t subordinate_bus;
if (!dev) { if (!dev) {
@ -570,13 +581,13 @@ vmd_bus_update_bridge_info(vmd_pci_device *bridge)
} }
static bool static bool
vmd_is_supported_device(vmd_pci_device *dev) vmd_is_supported_device(struct vmd_pci_device *dev)
{ {
return dev->class == PCI_CLASS_STORAGE_EXPRESS; return dev->class == PCI_CLASS_STORAGE_EXPRESS;
} }
static void static void
vmd_dev_init(vmd_pci_device *dev) vmd_dev_init(struct vmd_pci_device *dev)
{ {
uint8_t bdf[32]; uint8_t bdf[32];
@ -608,13 +619,14 @@ vmd_dev_init(vmd_pci_device *dev)
* Return count of how many devices found(type1 + type 0 header devices) * Return count of how many devices found(type1 + type 0 header devices)
*/ */
static uint8_t static uint8_t
vmd_scan_single_bus(vmd_pci_bus *bus, vmd_pci_device *parent_bridge) vmd_scan_single_bus(struct vmd_pci_bus *bus, struct vmd_pci_device *parent_bridge)
{ {
/* assuming only single function devices are on the bus */ /* assuming only single function devices are on the bus */
vmd_pci_device *new_dev; struct vmd_pci_device *new_dev;
vmd_pci_bus *new_bus; struct vmd_adapter *vmd;
int device_number, dev_cnt = 0; union express_slot_capabilities_register slot_cap;
express_slot_capabiliies_register slot_cap; struct vmd_pci_bus *new_bus;
uint8_t device_number, dev_cnt = 0;
uint8_t new_bus_num; uint8_t new_bus_num;
for (device_number = 0; device_number < 32; device_number++) { for (device_number = 0; device_number < 32; device_number++) {
@ -677,7 +689,7 @@ vmd_scan_single_bus(vmd_pci_bus *bus, vmd_pci_device *parent_bridge)
vmd_setup_msix(new_dev, &bus->vmd->msix_table[0]); vmd_setup_msix(new_dev, &bus->vmd->msix_table[0]);
vmd_dev_init(new_dev); vmd_dev_init(new_dev);
if (vmd_is_supported_device(new_dev)) { if (vmd_is_supported_device(new_dev)) {
vmd_adapter *vmd = bus->vmd; vmd = bus->vmd;
vmd->target[vmd->nvme_count] = new_dev; vmd->target[vmd->nvme_count] = new_dev;
vmd->nvme_count++; vmd->nvme_count++;
} }
@ -695,7 +707,7 @@ vmd_scan_single_bus(vmd_pci_bus *bus, vmd_pci_device *parent_bridge)
} }
static void static void
vmd_print_pci_info(vmd_pci_device *dev) vmd_print_pci_info(struct vmd_pci_device *dev)
{ {
if (!dev) { if (!dev) {
return; return;
@ -740,9 +752,10 @@ vmd_print_pci_info(vmd_pci_device *dev)
} }
static void static void
vmd_pci_print(vmd_pci_bus *bus_list) vmd_pci_print(struct vmd_pci_bus *bus_list)
{ {
vmd_pci_bus *bus = bus_list; struct vmd_pci_bus *bus = bus_list;
struct vmd_pci_device *dev;
SPDK_INFOLOG(SPDK_LOG_VMD, "\n ...PCIE devices attached to VMD %04x:%02x:%02x:%x...\n", SPDK_INFOLOG(SPDK_LOG_VMD, "\n ...PCIE devices attached to VMD %04x:%02x:%02x:%x...\n",
bus_list->vmd->pci.addr.domain, bus_list->vmd->pci.addr.bus, bus_list->vmd->pci.addr.domain, bus_list->vmd->pci.addr.bus,
@ -751,7 +764,7 @@ vmd_pci_print(vmd_pci_bus *bus_list)
while (bus != NULL) { while (bus != NULL) {
vmd_print_pci_info(bus->self); vmd_print_pci_info(bus->self);
vmd_pci_device *dev = bus->dev_list; dev = bus->dev_list;
while (dev != NULL) { while (dev != NULL) {
vmd_print_pci_info(dev); vmd_print_pci_info(dev);
dev = dev->next; dev = dev->next;
@ -761,27 +774,26 @@ vmd_pci_print(vmd_pci_bus *bus_list)
} }
static uint8_t static uint8_t
vmd_scan_pcibus(vmd_pci_bus *bus) vmd_scan_pcibus(struct vmd_pci_bus *bus)
{ {
vmd_pci_bus *new_bus = bus; uint8_t dev_cnt;
int dev_cnt;
g_end_device_count = 0; g_end_device_count = 0;
vmd_add_bus_to_list(bus->vmd, new_bus); vmd_add_bus_to_list(bus->vmd, bus);
bus->vmd->next_bus_number = bus->bus_number + 1; bus->vmd->next_bus_number = bus->bus_number + 1;
dev_cnt = vmd_scan_single_bus(new_bus, NULL); dev_cnt = vmd_scan_single_bus(bus, NULL);
SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %d devices\n", dev_cnt); SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %u devices\n", dev_cnt);
SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %d END DEVICES\n", g_end_device_count); SPDK_DEBUGLOG(SPDK_LOG_VMD, "\tVMD scan found %u END DEVICES\n", g_end_device_count);
vmd_pci_print(bus->vmd->bus_list); vmd_pci_print(bus->vmd->bus_list);
return (uint8_t)dev_cnt; return dev_cnt;
} }
static int static int
vmd_map_bars(vmd_adapter *vmd, struct spdk_pci_device *dev) vmd_map_bars(struct vmd_adapter *vmd, struct spdk_pci_device *dev)
{ {
int rc = spdk_pci_device_map_bar(dev, 0, (void **)&vmd->cfg_vaddr, int rc = spdk_pci_device_map_bar(dev, 0, (void **)&vmd->cfg_vaddr,
&vmd->cfgbar, &vmd->cfgbar_size); &vmd->cfgbar, &vmd->cfgbar_size);
@ -803,7 +815,7 @@ vmd_map_bars(vmd_adapter *vmd, struct spdk_pci_device *dev)
} }
static int static int
vmd_enumerate_devices(vmd_adapter *vmd) vmd_enumerate_devices(struct vmd_adapter *vmd)
{ {
vmd->vmd_bus.vmd = vmd; vmd->vmd_bus.vmd = vmd;
vmd->vmd_bus.secondary_bus = vmd->vmd_bus.subordinate_bus = 0; vmd->vmd_bus.secondary_bus = vmd->vmd_bus.subordinate_bus = 0;
@ -868,6 +880,8 @@ int
spdk_vmd_pci_device_list(struct spdk_pci_addr vmd_addr, struct spdk_pci_device *nvme_list) spdk_vmd_pci_device_list(struct spdk_pci_addr vmd_addr, struct spdk_pci_device *nvme_list)
{ {
int cnt = 0; int cnt = 0;
struct vmd_pci_bus *bus;
struct vmd_pci_device *dev;
if (!nvme_list) { if (!nvme_list) {
return -1; return -1;
@ -875,9 +889,9 @@ spdk_vmd_pci_device_list(struct spdk_pci_addr vmd_addr, struct spdk_pci_device *
for (int i = 0; i < MAX_VMD_TARGET; ++i) { for (int i = 0; i < MAX_VMD_TARGET; ++i) {
if (spdk_pci_addr_compare(&vmd_addr, &g_vmd_container.vmd[i].pci.addr) == 0) { if (spdk_pci_addr_compare(&vmd_addr, &g_vmd_container.vmd[i].pci.addr) == 0) {
vmd_pci_bus *bus = g_vmd_container.vmd[i].bus_list; bus = g_vmd_container.vmd[i].bus_list;
while (bus != NULL) { while (bus != NULL) {
vmd_pci_device *dev = bus->dev_list; dev = bus->dev_list;
while (dev != NULL) { while (dev != NULL) {
nvme_list[cnt++] = dev->pci; nvme_list[cnt++] = dev->pci;
if (!dev->is_hooked) { if (!dev->is_hooked) {

59
lib/vmd/vmd.h
View File

@ -45,9 +45,15 @@ struct vmd_hot_plug;
struct vmd_adapter; struct vmd_adapter;
struct vmd_pci_device; struct vmd_pci_device;
typedef struct vmd_pci_bus { struct pci_bars {
uint64_t vaddr;
uint64_t start;
uint32_t size;
};
struct vmd_pci_bus {
struct vmd_adapter *vmd; struct vmd_adapter *vmd;
struct vmd_pci_bus *parent; /* parent bus that this bus is attached to(primary bus. */ struct vmd_pci_bus *parent; /* parent bus that this bus is attached to(primary bus. */
struct vmd_pci_device *self; /* Pci device that describes this bus(bar, bus numbers, etc */ struct vmd_pci_device *self; /* Pci device that describes this bus(bar, bus numbers, etc */
uint32_t domain : 8; uint32_t domain : 8;
@ -63,22 +69,22 @@ typedef struct vmd_pci_bus {
struct vmd_pci_device *dev_list; /* list of pci end device attached to this bus */ struct vmd_pci_device *dev_list; /* list of pci end device attached to this bus */
struct vmd_pci_bus *next; /* link for all buses found during scan */ struct vmd_pci_bus *next; /* link for all buses found during scan */
} vmd_pci_bus; };
typedef struct vmd_pci_device { struct vmd_pci_device {
struct spdk_pci_device pci; struct spdk_pci_device pci;
struct pci_bars bar[6]; struct pci_bars bar[6];
struct vmd_pci_device *parent_bridge, *next; struct vmd_pci_device *parent_bridge, *next;
vmd_pci_bus *bus, *parent; struct vmd_pci_bus *bus, *parent;
vmd_pci_bus *bus_object; /* bus tracks pci bus associated with this dev if type 1 dev. */ struct vmd_pci_bus *bus_object; /* bus tracks pci bus associated with this dev if type 1 dev. */
vmd_pci_bus *subordinate; struct vmd_pci_bus *subordinate;
volatile pci_header *header; volatile struct pci_header *header;
volatile pci_express_cap *pcie_cap; volatile struct pci_express_cap *pcie_cap;
volatile pci_msix_capability *msix_cap; volatile struct pci_msix_capability *msix_cap;
volatile pci_msi_cap *msi_cap; volatile struct pci_msi_cap *msi_cap;
volatile serial_number_capability *sn_cap; volatile struct serial_number_capability *sn_cap;
volatile pci_msix_table_entry *msix_table; volatile struct pci_msix_table_entry *msix_table;
uint32_t class; uint32_t class;
uint16_t vid; uint16_t vid;
@ -95,7 +101,7 @@ typedef struct vmd_pci_device {
uint32_t target : 16; uint32_t target : 16;
struct vmd_hot_plug *hp; struct vmd_hot_plug *hp;
} vmd_pci_device; };
/* /*
@ -108,23 +114,23 @@ struct pci_mem_mgr {
uint64_t addr; uint64_t addr;
}; };
typedef struct vmd_hot_plug { struct vmd_hot_plug {
uint32_t count : 12; uint32_t count : 12;
uint32_t reserved_bus_count : 4; uint32_t reserved_bus_count : 4;
uint32_t max_hotplug_bus_number : 8; uint32_t max_hotplug_bus_number : 8;
uint32_t next_bus_number : 8; uint32_t next_bus_number : 8;
uint32_t addr_size; uint32_t addr_size;
uint64_t physical_addr; uint64_t physical_addr;
express_slot_status_register slot_status; union express_slot_status_register slot_status;
struct pci_mem_mgr mem[ADDR_ELEM_COUNT]; struct pci_mem_mgr mem[ADDR_ELEM_COUNT];
uint8_t bus_numbers[RESERVED_HOTPLUG_BUSES]; uint8_t bus_numbers[RESERVED_HOTPLUG_BUSES];
vmd_pci_bus *bus; struct vmd_pci_bus *bus;
} vmd_hot_plug; };
/* /*
* The VMD adapter * The VMD adapter
*/ */
typedef struct vmd_adapter { struct vmd_adapter {
struct spdk_pci_device pci; struct spdk_pci_device pci;
uint32_t domain; uint32_t domain;
/* physical and virtual VMD bars */ /* physical and virtual VMD bars */
@ -132,9 +138,9 @@ typedef struct vmd_adapter {
uint64_t membar, membar_size; uint64_t membar, membar_size;
uint64_t msixbar, msixbar_size; uint64_t msixbar, msixbar_size;
volatile uint8_t *cfg_vaddr; volatile uint8_t *cfg_vaddr;
volatile uint8_t *mem_vaddr; volatile uint8_t *mem_vaddr;
volatile uint8_t *msix_vaddr; volatile uint8_t *msix_vaddr;
volatile struct _pci_misx_table_entry *msix_table; volatile struct pci_msix_table_entry *msix_table;
uint32_t bar_sizes[6]; uint32_t bar_sizes[6];
uint64_t physical_addr; uint64_t physical_addr;
@ -157,12 +163,11 @@ typedef struct vmd_adapter {
struct vmd_pci_bus vmd_bus, *bus_list; struct vmd_pci_bus vmd_bus, *bus_list;
struct event_fifo *hp_queue; struct event_fifo *hp_queue;
};
} vmd_adapter;
/* TODO: Temporary stubs for Hot Plug interface */ /* TODO: Temporary stubs for Hot Plug interface */
static inline vmd_pci_bus * static inline struct vmd_pci_bus *
vmd_is_dev_in_hotplug_path(vmd_pci_device *dev) vmd_is_dev_in_hotplug_path(struct vmd_pci_device *dev)
{ {
return NULL; return NULL;
} }
@ -181,7 +186,7 @@ vmd_hp_enable_hotplug(struct vmd_hot_plug *hp)
} }
static inline struct vmd_hot_plug * static inline struct vmd_hot_plug *
vmd_new_hotplug(vmd_pci_bus *newBus, uint8_t reservedBuses) vmd_new_hotplug(struct vmd_pci_bus *newBus, uint8_t reservedBuses)
{ {
return NULL; return NULL;
} }

271
lib/vmd/vmd_spec.h
View File

@ -116,19 +116,19 @@
#define BAR_SIZE (1 << 20) #define BAR_SIZE (1 << 20)
typedef struct _enhanced_capability_hdr { struct pci_enhanced_capability_header {
uint16_t capability_id; uint16_t capability_id;
uint16_t version: 4; uint16_t version: 4;
uint16_t next: 12; uint16_t next: 12;
} pci_enhanced_capability_header; };
typedef struct _SerialNumberCapability { struct serial_number_capability {
pci_enhanced_capability_header hdr; struct pci_enhanced_capability_header hdr;
uint32_t sn_low; uint32_t sn_low;
uint32_t sn_hi; uint32_t sn_hi;
} serial_number_capability; };
typedef struct _PciHeaderCommon { struct pci_header_common {
uint16_t vendor_id; uint16_t vendor_id;
uint16_t device_id; uint16_t device_id;
uint16_t command; uint16_t command;
@ -144,9 +144,9 @@ typedef struct _PciHeaderCommon {
uint8_t int_line; uint8_t int_line;
uint8_t int_pin; uint8_t int_pin;
uint8_t rsvd62[2]; uint8_t rsvd62[2];
} pci_header_common; };
typedef struct _PciTypeZeroHeader { struct pci_header_zero {
uint16_t vendor_id; uint16_t vendor_id;
uint16_t device_id; uint16_t device_id;
uint16_t command; uint16_t command;
@ -167,9 +167,9 @@ typedef struct _PciTypeZeroHeader {
uint8_t int_pin; uint8_t int_pin;
uint8_t min_gnt; uint8_t min_gnt;
uint8_t max_lat; uint8_t max_lat;
} pci_header_zero; };
typedef struct _PciTypeOneHeader { struct pci_header_one {
uint16_t vendor_id; uint16_t vendor_id;
uint16_t device_id; uint16_t device_id;
uint16_t command; uint16_t command;
@ -201,13 +201,12 @@ typedef struct _PciTypeOneHeader {
uint8_t int_line; uint8_t int_line;
uint8_t int_pin; uint8_t int_pin;
uint16_t bridge_control; uint16_t bridge_control;
} pci_header_one; };
struct pci_capabilities_header {
typedef struct _PciCapHdr {
uint8_t capability_id; uint8_t capability_id;
uint8_t next; uint8_t next;
} pci_capabilities_header; };
/* /*
* MSI capability structure for msi interrupt vectors * MSI capability structure for msi interrupt vectors
@ -216,8 +215,8 @@ typedef struct _PciCapHdr {
#define MSIX_ENTRY_VECTOR_CTRL_MASKBIT 1 #define MSIX_ENTRY_VECTOR_CTRL_MASKBIT 1
#define PORT_INT_VECTOR 0; #define PORT_INT_VECTOR 0;
#define CLEAR_MSIX_DESTINATION_ID 0xfff00fff #define CLEAR_MSIX_DESTINATION_ID 0xfff00fff
struct PCI_MSI_CAPABILITY { struct pci_msi_cap {
pci_capabilities_header header; struct pci_capabilities_header header;
union _MsiControl { union _MsiControl {
uint16_t as_uint16_t; uint16_t as_uint16_t;
struct _PCI_MSI_MESSAGE_CONTROL { struct _PCI_MSI_MESSAGE_CONTROL {
@ -249,9 +248,8 @@ struct PCI_MSI_CAPABILITY {
} option64_bit; } option64_bit;
}; };
}; };
typedef struct PCI_MSI_CAPABILITY pci_msi_cap;
typedef struct PcixTablePointer { struct pcix_table_pointer {
union { union {
struct { struct {
uint32_t BaseIndexRegister : 3; uint32_t BaseIndexRegister : 3;
@ -259,10 +257,10 @@ typedef struct PcixTablePointer {
} TableBIR; } TableBIR;
uint32_t TableOffset; uint32_t TableOffset;
}; };
} pcix_table_pointer; };
typedef struct _PciMsixCapability { struct pci_msix_capability {
struct _PciCapHdr header; struct pci_capabilities_header header;
union _MsixControl { union _MsixControl {
uint16_t as_uint16_t; uint16_t as_uint16_t;
struct msg_ctrl { struct msg_ctrl {
@ -273,34 +271,43 @@ typedef struct _PciMsixCapability {
} bit; } bit;
} message_control; } message_control;
pcix_table_pointer message_table; struct pcix_table_pointer message_table;
pcix_table_pointer pba_table; struct pcix_table_pointer pba_table;
} pci_msix_capability; };
typedef struct _pci_misx_table_entry { struct pci_msix_table_entry {
volatile uint32_t message_addr_lo; volatile uint32_t message_addr_lo;
volatile uint32_t message_addr_hi; volatile uint32_t message_addr_hi;
volatile uint32_t message_data; volatile uint32_t message_data;
volatile uint32_t vector_control; volatile uint32_t vector_control;
} pci_msix_table_entry; };
/* /*
* Pci express capability * Pci express capability
*/ */
enum PciExpressCapabilities { enum PciExpressCapabilities {
LegacyEndpoint = 0x1, /* 0001b Legacy PCI Express Endpoint */ /* 0001b Legacy PCI Express Endpoint */
ExpressEndpoint = 0x0, /* 0000b PCI Express Endpoint */ LegacyEndpoint = 0x1,
RootComplexRootPort = 0x4, /* 0100b Root Port of PCI Express Root Complex* */ /* 0000b PCI Express Endpoint */
SwitchUpstreamPort = 0x5, /* 0101b Upstream Port of PCI Express Switch* */ ExpressEndpoint = 0x0,
SwitchDownStreamPort = 0x6, /* 0110b Downstream Port of PCI Express Switch* */ /* 0100b Root Port of PCI Express Root Complex* */
ExpressToPciBridge = 0x7, /* 0111b PCI Express to PCI/PCI-X Bridge* */ RootComplexRootPort = 0x4,
PciToExpressBridge = 0x8, /* 1000b PCI/PCI-X to PCI Express Bridge* */ /* 0101b Upstream Port of PCI Express Switch* */
RCIntegratedEndpoint = 0x9, /* 1001b Root Complex Integrated Endpoint */ SwitchUpstreamPort = 0x5,
RootComplexEventCollector = 0xa, /* 1010b Root Complex Event Collector */ /* 0110b Downstream Port of PCI Express Switch* */
SwitchDownStreamPort = 0x6,
/* 0111b PCI Express to PCI/PCI-X Bridge* */
ExpressToPciBridge = 0x7,
/* 1000b PCI/PCI-X to PCI Express Bridge* */
PciToExpressBridge = 0x8,
/* 1001b Root Complex Integrated Endpoint */
RCIntegratedEndpoint = 0x9,
/* 1010b Root Complex Event Collector */
RootComplexEventCollector = 0xa,
InvalidCapability = 0xff InvalidCapability = 0xff
}; };
typedef union _EXPRESS_CAPABILITIES_REGISTER { union express_capability_register {
struct { struct {
uint16_t capability_version : 4; uint16_t capability_version : 4;
uint16_t device_type : 4; uint16_t device_type : 4;
@ -309,116 +316,9 @@ typedef union _EXPRESS_CAPABILITIES_REGISTER {
uint16_t rsv : 2; uint16_t rsv : 2;
} bit_field; } bit_field;
uint16_t as_uint16_t; uint16_t as_uint16_t;
} express_capability_register; };
typedef union _EXPRESS_DEVICE_CAPABILITIES_REGISTER { union express_slot_capabilities_register {
struct {
uint32_t max_payload_size_supported : 3;
uint32_t phantom_functions_supported : 2;
uint32_t extended_tag_supported : 1;
uint32_t L0s_acceptable_latency : 3;
uint32_t L1_acceptable_latency : 3;
uint32_t undefined : 3;
uint32_t role_based_error_reporting : 1;
uint32_t rsvd1 : 2;
uint32_t captured_slot_power_limit : 8;
uint32_t captured_slot_power_limit_scale : 2;
uint32_t rsvd2 : 4;
} bit_field;
uint32_t as_uint32_t;
} express_device_capability_register;
/*
* The low 3 bits of the PCI Express device control register dictate whether
* a device that implements AER routes error messages to the root complex.
* This mask is used when programming the AER bits in the device control
* register.
*/
#define EXPRESS_AER_DEVICE_CONTROL_MASK 0x07;
typedef union _EXPRESS_DEVICE_CONTROL_REGISTER {
struct {
uint16_t correctable_error_enable : 1;
uint16_t non_fatal_error_enable : 1;
uint16_t fatal_error_enable : 1;
uint16_t unsupported_request_error_enable : 1;
uint16_t enable_relaxed_order : 1;
uint16_t max_payload_size : 3;
uint16_t extended_tag_enable : 1;
uint16_t phantom_functions_enable : 1;
uint16_t aux_power_enable : 1;
uint16_t no_snoop_enable : 1;
uint16_t max_read_request_size : 3;
uint16_t bridge_config_retry_enable : 1;
} bit_field;
uint16_t as_uint16_t;;
} express_device_control_register;
/*
* The low 4 bits of the PCI Express device status register hold AER device
* status. This mask is used when programming the AER bits in the device status
* register.
*/
#define EXPRESS_AER_DEVICE_STATUS_MASK 0x0F;
typedef union _EXPRESS_DEVICE_STATUS_REGISTER {
struct {
uint16_t CorrectableErrorDetected : 1;
uint16_t NonFatalErrorDetected : 1;
uint16_t FatalErrorDetected : 1;
uint16_t UnsupportedRequestDetected : 1;
uint16_t AuxPowerDetected : 1;
uint16_t TransactionsPending : 1;
uint16_t Rsvd : 10;
} bit_field;
uint16_t Asuint16_t;
} express_device_status_register;
typedef union _EXPRESS_LINK_CAPABILITIES_REGISTER {
struct {
uint32_t MaximumLinkSpeed : 4;
uint32_t MaximumLinkWidth : 6;
uint32_t ActiveStatePMSupport : 2;
uint32_t L0sExitLatency : 3;
uint32_t L1ExitLatency : 3;
uint32_t ClockPowerManagement : 1;
uint32_t SurpriseDownErrorReportingCapable : 1;
uint32_t DataLinkLayerActiveReportingCapable : 1;
uint32_t LinkBandwidthNotificationCapability : 1;
uint32_t AspmOptionalityCompliance : 1;
uint32_t Rsvd : 1;
uint32_t PortNumber : 8;
} bit_field;
uint32_t Asuint32_t;
} express_link_capability_register;
typedef union _EXPRESS_LINK_CONTROL_REGISTER {
struct {
uint16_t ActiveStatePMControl : 2;
uint16_t Rsvd1 : 1;
uint16_t ReadCompletionBoundary : 1;
uint16_t LinkDisable : 1;
uint16_t RetrainLink : 1;
uint16_t CommonClockConfig : 1;
uint16_t ExtendedSynch : 1;
uint16_t EnableClockPowerManagement : 1;
uint16_t Rsvd2 : 7;
} bit_field;
uint16_t Asuint16_t;
} express_link_control_register;
typedef union _EXPRESS_LINK_STATUS_REGISTER {
struct {
uint16_t LinkSpeed : 4;
uint16_t LinkWidth : 6;
uint16_t Undefined : 1;
uint16_t LinkTraining : 1;
uint16_t SlotClockConfig : 1;
uint16_t DataLinkLayerActive : 1;
uint16_t Rsvd : 2;
} bitField;
uint16_t Asuint16_t;
} express_link_status_register;
typedef union _EXPRESS_SLOT_CAPABILITIES_REGISTER {
struct { struct {
uint32_t attention_button_present : 1; uint32_t attention_button_present : 1;
uint32_t power_controller_present : 1; uint32_t power_controller_present : 1;
@ -434,9 +334,9 @@ typedef union _EXPRESS_SLOT_CAPABILITIES_REGISTER {
uint32_t physical_slot_number : 13; uint32_t physical_slot_number : 13;
} bit_field; } bit_field;
uint32_t as_uint32_t; uint32_t as_uint32_t;
} express_slot_capabiliies_register; };
typedef union _EXPRESS_SLOT_CONTROL_REGISTER { union express_slot_control_register {
struct { struct {
uint16_t attention_button_enable : 1; uint16_t attention_button_enable : 1;
uint16_t power_fault_detect_enable : 1; uint16_t power_fault_detect_enable : 1;
@ -452,9 +352,9 @@ typedef union _EXPRESS_SLOT_CONTROL_REGISTER {
uint16_t Rsvd : 3; uint16_t Rsvd : 3;
} bit_field; } bit_field;
uint16_t as_uint16_t; uint16_t as_uint16_t;
} express_slot_control_register; };
typedef union _EXPRESS_SLOT_STATUS_REGISTER { union express_slot_status_register {
struct { struct {
uint16_t attention_button_pressed : 1; uint16_t attention_button_pressed : 1;
uint16_t power_fault_detected : 1; uint16_t power_fault_detected : 1;
@ -468,9 +368,9 @@ typedef union _EXPRESS_SLOT_STATUS_REGISTER {
uint16_t rsvd : 7; uint16_t rsvd : 7;
} bit_field; } bit_field;
uint16_t as_uint16_t; uint16_t as_uint16_t;
} express_slot_status_register; };
typedef union _EXPRESS_ROOT_CONTROL_REGISTER { union express_root_control_register {
struct { struct {
uint16_t CorrectableSerrEnable : 1; uint16_t CorrectableSerrEnable : 1;
uint16_t NonFatalSerrEnable : 1; uint16_t NonFatalSerrEnable : 1;
@ -482,52 +382,45 @@ typedef union _EXPRESS_ROOT_CONTROL_REGISTER {
uint16_t as_uint16_t; uint16_t as_uint16_t;
} express_root_control_register; } express_root_control_register;
struct pci_express_cap {
typedef struct _PciExpressCap { uint8_t capid;
uint8_t capid; uint8_t next_cap;
uint8_t next_cap; union express_capability_register express_cap_register;
express_capability_register express_cap_register; uint32_t device_cap;
uint32_t device_cap; uint16_t device_control;
uint16_t device_control; uint16_t device_status;
uint16_t device_status; uint32_t link_cap;
uint32_t link_cap; uint16_t link_control;
uint16_t link_control; uint16_t link_status;
uint16_t link_status; union express_slot_capabilities_register slot_cap;
express_slot_capabiliies_register slot_cap; union express_slot_control_register slot_control;
express_slot_control_register slot_control; union express_slot_status_register slot_status;
express_slot_status_register slot_status;
uint32_t root_status; uint32_t root_status;
uint32_t deviceCap2; uint32_t deviceCap2;
uint16_t deviceControl2; uint16_t deviceControl2;
uint16_t deviceStatus2; uint16_t deviceStatus2;
uint32_t linkCap2; uint32_t linkCap2;
uint16_t linkControl2; uint16_t linkControl2;
uint16_t linkStatus2; uint16_t linkStatus2;
uint32_t slotCap2; uint32_t slotCap2;
uint16_t slotControl2; uint16_t slotControl2;
uint16_t slotStatus2; uint16_t slotStatus2;
} pci_express_cap; };
typedef struct _PciMsixCap { struct pci_msix_cap {
uint8_t cap_idd; uint8_t cap_idd;
uint8_t next_cap; uint8_t next_cap;
uint16_t msg_control_reg; uint16_t msg_control_reg;
uint32_t msix_table_offset; uint32_t msix_table_offset;
uint32_t pba_offset; uint32_t pba_offset;
} pci_msix_cap; };
typedef struct _PciHeader { struct pci_header {
union { union {
pci_header_common common; struct pci_header_common common;
pci_header_zero zero; struct pci_header_zero zero;
pci_header_one one; struct pci_header_one one;
}; };
} pci_header;
struct pci_bars {
uint64_t vaddr;
uint64_t start;
uint32_t size;
}; };
#endif /* VMD_SPEC_H */ #endif /* VMD_SPEC_H */