From c65210d034347bdfd6ece33142f013efc085bb58 Mon Sep 17 00:00:00 2001 From: GangCao Date: Tue, 21 Jun 2016 16:37:15 -0400 Subject: [PATCH] nvme: return error immediately when enabling controller failed Change-Id: Id9cf6873cc831bd5099df49db95ef5073badf461 Signed-off-by: GangCao --- lib/nvme/nvme_ctrlr.c | 8 ++++---- test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/lib/nvme/nvme_ctrlr.c b/lib/nvme/nvme_ctrlr.c index 4f9dae813..7f4f2ced3 100644 --- a/lib/nvme/nvme_ctrlr.c +++ b/lib/nvme/nvme_ctrlr.c @@ -864,9 +864,9 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) /* * Controller is currently disabled. We can jump straight to enabling it. */ - nvme_ctrlr_enable(ctrlr); + rc = nvme_ctrlr_enable(ctrlr); nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms); - return 0; + return rc; } break; @@ -883,9 +883,9 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0: if (csts.bits.rdy == 0) { /* CC.EN = 0 && CSTS.RDY = 0, so we can enable the controller now. */ - nvme_ctrlr_enable(ctrlr); + rc = nvme_ctrlr_enable(ctrlr); nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms); - return 0; + return rc; } break; diff --git a/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c b/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c index 10b0a14c0..21018ce26 100644 --- a/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c +++ b/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c @@ -455,7 +455,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -473,7 +473,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -491,7 +491,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -593,7 +593,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -611,7 +611,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -692,7 +692,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); @@ -730,7 +730,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); - CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); + CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);