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nvme: remove DELAY_BEFORE_ENABLE quirk and always wait 100us

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A 100us is so small that applying the quirk to the specific
SSDs that require the delay is more trouble than it is worth.
So remove the quirk and always wait 100us before re-enabling
the NVMe SSD during initialization.

Signed-off-by: Jim Harris <james.r.harris@intel.com>
Change-Id: Id6a8cc6e35d103fffdf135580301fc3e5b27e722
This commit is contained in:
Jim Harris 2017-04-14 16:38:03 -07:00 committed by Ben Walker
parent c3c851f677
commit b5b9410da3
5 changed files with 11 additions and 16 deletions
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11
lib/nvme/nvme_ctrlr.c
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@ -1207,12 +1207,11 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
if (csts.bits.rdy == 0) { if (csts.bits.rdy == 0) {
SPDK_TRACELOG(SPDK_TRACE_NVME, "CC.EN = 0 && CSTS.RDY = 0\n"); SPDK_TRACELOG(SPDK_TRACE_NVME, "CC.EN = 0 && CSTS.RDY = 0\n");
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms); nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
/*
if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_ENABLE) { * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
SPDK_TRACELOG(SPDK_TRACE_NVME, "Applying quirk: Delay 100us before enabling.\n"); * set to 1 if it is too soon after CSTS.RDY is reported as 0.
ctrlr->sleep_timeout_tsc = spdk_get_ticks() + spdk_get_ticks_hz() / 10000; */
} spdk_delay_us(100);
return 0; return 0;
} }
break; break;

7
lib/nvme/nvme_internal.h
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@ -89,13 +89,6 @@
*/ */
#define NVME_INTEL_QUIRK_STRIPING 0x8 #define NVME_INTEL_QUIRK_STRIPING 0x8
/*
* A small delay is required before re-enabling a controller.
* The delay required is often vanishingly small, such that
* many drivers do not ever encounter the problem.
*/
#define NVME_QUIRK_DELAY_BEFORE_ENABLE 0x10
#define NVME_MAX_ASYNC_EVENTS (8) #define NVME_MAX_ASYNC_EVENTS (8)
#define NVME_MIN_TIMEOUT_PERIOD (5) #define NVME_MIN_TIMEOUT_PERIOD (5)

3
lib/nvme/nvme_quirks.c
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@ -42,8 +42,7 @@ static const struct nvme_quirk nvme_quirks[] = {
{ {SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID}, { {SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_READ_LATENCY |
NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY |
NVME_INTEL_QUIRK_STRIPING | NVME_INTEL_QUIRK_STRIPING
NVME_QUIRK_DELAY_BEFORE_ENABLE
}, },
{ {SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID}, { {SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
NVME_INTEL_QUIRK_STRIPING NVME_INTEL_QUIRK_STRIPING

1
test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c
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@ -50,7 +50,6 @@ struct nvme_driver _g_nvme_driver = {
.lock = PTHREAD_MUTEX_INITIALIZER, .lock = PTHREAD_MUTEX_INITIALIZER,
}; };
uint64_t g_ut_tsc = 0;
struct spdk_nvme_registers g_ut_nvme_regs = {}; struct spdk_nvme_registers g_ut_nvme_regs = {};
__thread int nvme_thread_ioq_index = -1; __thread int nvme_thread_ioq_index = -1;

5
test/lib/test_env.c
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@ -157,6 +157,11 @@ uint64_t spdk_get_ticks_hz(void)
return 1000000; return 1000000;
} }
void spdk_delay_us(unsigned int us)
{
ut_tsc += us;
}
int int
spdk_pci_addr_parse(struct spdk_pci_addr *addr, const char *bdf) spdk_pci_addr_parse(struct spdk_pci_addr *addr, const char *bdf)
{ {