From ad9ccbbf52d62dca3e3b4a80ff8ecd8293b8f942 Mon Sep 17 00:00:00 2001
From: Konrad Sztyber <konrad.sztyber@intel.com>
Date: Tue, 2 Mar 2021 08:30:48 +0100
Subject: [PATCH] external_code/nvme: controller register access functions

Added getters/setters providing access to several of the NVMe
controller's registers.  Only the registers that are needed for the
initialization are implemented.

For now all of them are unused, so they're marked as external to avoid
the -Wunused-function warnings.  The subsequent patches will make use of
them and mark as static appropriately.

Signed-off-by: Konrad Sztyber <konrad.sztyber@intel.com>
Change-Id: I7012583f74e87720f6915afca69474ad1bb1e377
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6668
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Community-CI: Mellanox Build Bot
Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
---
 test/external_code/nvme/nvme.c | 92 ++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/test/external_code/nvme/nvme.c b/test/external_code/nvme/nvme.c
index bf3530742..f13534883 100644
--- a/test/external_code/nvme/nvme.c
+++ b/test/external_code/nvme/nvme.c
@@ -31,6 +31,7 @@
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "spdk/mmio.h"
 #include "spdk/nvme_spec.h"
 #include "spdk/log.h"
 #include "spdk/stdinc.h"
@@ -74,6 +75,97 @@ find_ctrlr_by_addr(struct spdk_pci_addr *addr)
 	return NULL;
 }
 
+static volatile void *
+get_pcie_reg_addr(struct nvme_ctrlr *ctrlr, uint32_t offset)
+{
+	return (volatile void *)((uintptr_t)ctrlr->regs + offset);
+}
+
+static void
+get_pcie_reg_4(struct nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value)
+{
+	assert(offset <= sizeof(struct spdk_nvme_registers) - 4);
+	*value = spdk_mmio_read_4(get_pcie_reg_addr(ctrlr, offset));
+}
+
+static void
+get_pcie_reg_8(struct nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value)
+{
+	assert(offset <= sizeof(struct spdk_nvme_registers) - 8);
+	*value = spdk_mmio_read_8(get_pcie_reg_addr(ctrlr, offset));
+}
+
+static void
+set_pcie_reg_4(struct nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value)
+{
+	assert(offset <= sizeof(struct spdk_nvme_registers) - 4);
+	spdk_mmio_write_4(get_pcie_reg_addr(ctrlr, offset), value);
+}
+
+static void
+set_pcie_reg_8(struct nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value)
+{
+	assert(offset <= sizeof(struct spdk_nvme_registers) - 8);
+	spdk_mmio_write_8(get_pcie_reg_addr(ctrlr, offset), value);
+}
+
+void nvme_ctrlr_get_cap(struct nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap);
+
+void
+nvme_ctrlr_get_cap(struct nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
+{
+	get_pcie_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap), &cap->raw);
+}
+
+void
+nvme_ctrlr_get_cc(struct nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc);
+
+void
+nvme_ctrlr_get_cc(struct nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
+{
+	get_pcie_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc), &cc->raw);
+}
+
+void nvme_ctrlr_get_csts(struct nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts);
+
+void
+nvme_ctrlr_get_csts(struct nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
+{
+	get_pcie_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts), &csts->raw);
+}
+
+void nvme_ctrlr_set_cc(struct nvme_ctrlr *ctrlr, const union spdk_nvme_cc_register *cc);
+
+void
+nvme_ctrlr_set_cc(struct nvme_ctrlr *ctrlr, const union spdk_nvme_cc_register *cc)
+{
+	set_pcie_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw), cc->raw);
+}
+
+void nvme_ctrlr_set_asq(struct nvme_ctrlr *ctrlr, uint64_t value);
+
+void
+nvme_ctrlr_set_asq(struct nvme_ctrlr *ctrlr, uint64_t value)
+{
+	set_pcie_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, asq), value);
+}
+
+void nvme_ctrlr_set_acq(struct nvme_ctrlr *ctrlr, uint64_t value);
+
+void
+nvme_ctrlr_set_acq(struct nvme_ctrlr *ctrlr, uint64_t value)
+{
+	set_pcie_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, acq), value);
+}
+
+void nvme_ctrlr_set_aqa(struct nvme_ctrlr *ctrlr, const union spdk_nvme_aqa_register *aqa);
+
+void
+nvme_ctrlr_set_aqa(struct nvme_ctrlr *ctrlr, const union spdk_nvme_aqa_register *aqa)
+{
+	set_pcie_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, aqa.raw), aqa->raw);
+}
+
 static int
 pcie_enum_cb(void *ctx, struct spdk_pci_device *pci_dev)
 {