nvme: convert adminq to a qpair pointer
Rather than embedding adminq directly in the spdk_nvme_ctrlr structure, change it to a pointer to a spdk_nvme_qpair. This is necessary to allow the transport to extend the qpair structure. Change-Id: I041685d5037088cf56d046fe99bf204edcfc57b1 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
This commit is contained in:
parent
5ba51e5016
commit
a987bd16c2
@ -237,7 +237,7 @@ static int nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
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nvme_completion_poll_cb,
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nvme_completion_poll_cb,
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&status);
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&status);
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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spdk_free(log_page_directory);
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spdk_free(log_page_directory);
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@ -310,7 +310,12 @@ nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
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static int
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static int
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nvme_ctrlr_construct_admin_qpair(struct spdk_nvme_ctrlr *ctrlr)
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nvme_ctrlr_construct_admin_qpair(struct spdk_nvme_ctrlr *ctrlr)
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{
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{
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return nvme_qpair_construct(&ctrlr->adminq,
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ctrlr->adminq = spdk_zmalloc(sizeof(struct spdk_nvme_qpair), 64, NULL);
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if (ctrlr->adminq == NULL) {
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return -ENOMEM;
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}
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return nvme_qpair_construct(ctrlr->adminq,
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0, /* qpair ID */
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0, /* qpair ID */
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NVME_ADMIN_ENTRIES,
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NVME_ADMIN_ENTRIES,
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ctrlr);
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ctrlr);
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@ -322,7 +327,7 @@ nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
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struct spdk_nvme_qpair *qpair;
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struct spdk_nvme_qpair *qpair;
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ctrlr->is_failed = true;
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ctrlr->is_failed = true;
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nvme_qpair_fail(&ctrlr->adminq);
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nvme_qpair_fail(ctrlr->adminq);
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TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
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TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
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nvme_qpair_fail(qpair);
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nvme_qpair_fail(qpair);
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}
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}
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@ -393,20 +398,20 @@ nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
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return -EINVAL;
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return -EINVAL;
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}
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}
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if (nvme_ctrlr_set_asq(ctrlr, ctrlr->adminq.cmd_bus_addr)) {
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if (nvme_ctrlr_set_asq(ctrlr, ctrlr->adminq->cmd_bus_addr)) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "set_asq() failed\n");
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SPDK_TRACELOG(SPDK_TRACE_NVME, "set_asq() failed\n");
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return -EIO;
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return -EIO;
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}
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}
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if (nvme_ctrlr_set_acq(ctrlr, ctrlr->adminq.cpl_bus_addr)) {
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if (nvme_ctrlr_set_acq(ctrlr, ctrlr->adminq->cpl_bus_addr)) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "set_acq() failed\n");
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SPDK_TRACELOG(SPDK_TRACE_NVME, "set_acq() failed\n");
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return -EIO;
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return -EIO;
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}
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}
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aqa.raw = 0;
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aqa.raw = 0;
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/* acqs and asqs are 0-based. */
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/* acqs and asqs are 0-based. */
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aqa.bits.acqs = ctrlr->adminq.num_entries - 1;
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aqa.bits.acqs = ctrlr->adminq->num_entries - 1;
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aqa.bits.asqs = ctrlr->adminq.num_entries - 1;
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aqa.bits.asqs = ctrlr->adminq->num_entries - 1;
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if (nvme_ctrlr_set_aqa(ctrlr, &aqa)) {
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if (nvme_ctrlr_set_aqa(ctrlr, &aqa)) {
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SPDK_TRACELOG(SPDK_TRACE_NVME, "set_aqa() failed\n");
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SPDK_TRACELOG(SPDK_TRACE_NVME, "set_aqa() failed\n");
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@ -484,7 +489,7 @@ spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
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SPDK_NOTICELOG("resetting controller\n");
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SPDK_NOTICELOG("resetting controller\n");
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/* Disable all queues before disabling the controller hardware. */
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/* Disable all queues before disabling the controller hardware. */
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nvme_qpair_disable(&ctrlr->adminq);
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nvme_qpair_disable(ctrlr->adminq);
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TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
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TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
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nvme_qpair_disable(qpair);
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nvme_qpair_disable(qpair);
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}
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}
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@ -532,7 +537,7 @@ nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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SPDK_ERRLOG("nvme_identify_controller failed!\n");
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SPDK_ERRLOG("nvme_identify_controller failed!\n");
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@ -578,7 +583,7 @@ nvme_ctrlr_set_num_qpairs(struct spdk_nvme_ctrlr *ctrlr)
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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SPDK_ERRLOG("nvme_set_num_queues failed!\n");
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SPDK_ERRLOG("nvme_set_num_queues failed!\n");
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@ -747,7 +752,7 @@ nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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SPDK_ERRLOG("nvme_ctrlr_cmd_set_async_event_config failed!\n");
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SPDK_ERRLOG("nvme_ctrlr_cmd_set_async_event_config failed!\n");
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@ -890,9 +895,9 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
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int
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int
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nvme_ctrlr_start(struct spdk_nvme_ctrlr *ctrlr)
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nvme_ctrlr_start(struct spdk_nvme_ctrlr *ctrlr)
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{
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{
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ctrlr->transport->qpair_reset(&ctrlr->adminq);
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ctrlr->transport->qpair_reset(ctrlr->adminq);
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nvme_qpair_enable(&ctrlr->adminq);
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nvme_qpair_enable(ctrlr->adminq);
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if (nvme_ctrlr_identify(ctrlr) != 0) {
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if (nvme_ctrlr_identify(ctrlr) != 0) {
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return -1;
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return -1;
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@ -985,7 +990,10 @@ nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
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spdk_bit_array_free(&ctrlr->free_io_qids);
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spdk_bit_array_free(&ctrlr->free_io_qids);
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nvme_qpair_destroy(&ctrlr->adminq);
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if (ctrlr->adminq) {
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nvme_qpair_destroy(ctrlr->adminq);
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spdk_free(ctrlr->adminq);
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}
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pthread_mutex_destroy(&ctrlr->ctrlr_lock);
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pthread_mutex_destroy(&ctrlr->ctrlr_lock);
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@ -996,7 +1004,7 @@ int
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nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
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nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
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struct nvme_request *req)
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struct nvme_request *req)
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{
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{
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return nvme_qpair_submit_request(&ctrlr->adminq, req);
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return nvme_qpair_submit_request(ctrlr->adminq, req);
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}
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}
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int32_t
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int32_t
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@ -1005,7 +1013,7 @@ spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
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int32_t num_completions;
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int32_t num_completions;
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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num_completions = spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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num_completions = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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return num_completions;
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return num_completions;
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@ -1092,7 +1100,7 @@ spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
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return res;
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return res;
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -1117,7 +1125,7 @@ spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
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return res;
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return res;
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -1140,7 +1148,7 @@ spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_dat
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return 0;
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return 0;
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -1169,7 +1177,7 @@ spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
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return res;
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return res;
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -1194,7 +1202,7 @@ spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
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return res;
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return res;
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -1239,7 +1247,7 @@ spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, ui
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -1265,7 +1273,7 @@ spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, ui
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -465,7 +465,7 @@ struct spdk_nvme_ctrlr {
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pthread_mutex_t ctrlr_lock;
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pthread_mutex_t ctrlr_lock;
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struct spdk_nvme_qpair adminq;
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struct spdk_nvme_qpair *adminq;
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/**
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/**
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* Identify Controller data.
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* Identify Controller data.
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@ -56,7 +56,7 @@ int nvme_ns_identify_update(struct spdk_nvme_ns *ns)
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while (status.done == false) {
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while (status.done == false) {
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pthread_mutex_lock(&ns->ctrlr->ctrlr_lock);
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pthread_mutex_lock(&ns->ctrlr->ctrlr_lock);
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spdk_nvme_qpair_process_completions(&ns->ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ns->ctrlr->adminq, 0);
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pthread_mutex_unlock(&ns->ctrlr->ctrlr_lock);
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pthread_mutex_unlock(&ns->ctrlr->ctrlr_lock);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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@ -798,7 +798,7 @@ _nvme_pcie_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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SPDK_ERRLOG("nvme_create_io_cq failed!\n");
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SPDK_ERRLOG("nvme_create_io_cq failed!\n");
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@ -812,7 +812,7 @@ _nvme_pcie_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
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SPDK_ERRLOG("nvme_create_io_sq failed!\n");
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SPDK_ERRLOG("nvme_create_io_sq failed!\n");
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@ -823,7 +823,7 @@ _nvme_pcie_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme
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return -1;
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return -1;
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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return -1;
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return -1;
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}
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}
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@ -904,7 +904,7 @@ nvme_pcie_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_
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return rc;
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return rc;
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}
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}
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while (status.done == false) {
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while (status.done == false) {
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spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
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spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
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}
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}
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if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
||||||
return -1;
|
return -1;
|
||||||
@ -916,7 +916,7 @@ nvme_pcie_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_
|
|||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
while (status.done == false) {
|
while (status.done == false) {
|
||||||
spdk_nvme_qpair_process_completions(&ctrlr->adminq, 0);
|
spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
|
||||||
}
|
}
|
||||||
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
if (spdk_nvme_cpl_is_error(&status.cpl)) {
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -490,6 +490,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
|
|||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
|
||||||
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
|
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -508,6 +511,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -526,6 +532,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -544,6 +553,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -609,6 +621,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
|
|||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
|
||||||
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
|
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -629,6 +644,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
|
|||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
|
||||||
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR);
|
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -647,6 +665,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -665,6 +686,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -729,6 +753,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
|
|||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
|
||||||
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
|
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -747,6 +774,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -767,6 +797,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
|
|||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
|
||||||
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS);
|
CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
@ -785,6 +818,9 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void)
|
|||||||
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
|
||||||
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
|
||||||
|
|
||||||
|
g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;
|
||||||
|
nvme_ctrlr_destruct(&ctrlr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset to initial state
|
* Reset to initial state
|
||||||
*/
|
*/
|
||||||
|
Loading…
Reference in New Issue
Block a user