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external_code/nvme: initial controller initialization definitions

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After enumerating and attaching NVMe controllers, they're now
initialized at the end of nvme_probe()/nvme_connect().  For now, they're
immediately marked as initialized, but subsequent patches will replace
it with an actual initialization.

Signed-off-by: Konrad Sztyber <konrad.sztyber@intel.com>
Change-Id: I22137bb10e871c7e79c28053c8ec98a835e11147
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6672
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Community-CI: Mellanox Build Bot
Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
This commit is contained in:
Konrad Sztyber 2021-02-19 15:03:52 +01:00 committed by Tomasz Zawadzki
parent 07dc433a2f
commit a2d3ea8cb3
1 changed files with 49 additions and 5 deletions
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44
test/external_code/nvme/nvme.c
View File

@ -71,6 +71,27 @@ struct nvme_qpair {
uint32_t num_entries;
};
enum nvme_ctrlr_state {
/* Controller has not been initialized yet */
NVME_CTRLR_STATE_INIT,
/* Waiting for CSTS.RDY to transition from 0 to 1 so that CC.EN may be set to 0 */
NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
/* Waiting for CSTS.RDY to transition from 1 to 0 so that CC.EN may be set to 1 */
NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
/* Enable the controller by writing CC.EN to 1 */
NVME_CTRLR_STATE_ENABLE,
/* Waiting for CSTS.RDY to transition from 0 to 1 after enabling the controller */
NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
/* Identify Controller command will be sent to then controller */
NVME_CTRLR_STATE_IDENTIFY,
/* Waiting for Identify Controller command to be completed */
NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
/* Controller initialization has completed and the controller is ready */
NVME_CTRLR_STATE_READY,
/* Controller initialization error */
NVME_CTRLR_STATE_ERROR,
};
struct nvme_ctrlr {
/* Underlying PCI device */
struct spdk_pci_device *pci_device;
@ -82,6 +103,8 @@ struct nvme_ctrlr {
uint32_t page_size;
/* Admin queue pair */
struct nvme_qpair *admin_qpair;
/* State of the controller */
enum nvme_ctrlr_state state;
TAILQ_ENTRY(nvme_ctrlr) tailq;
};
@ -336,6 +359,15 @@ pcie_enum_cb(void *ctx, struct spdk_pci_device *pci_dev)
return 0;
}
static int
process_ctrlr_init(struct nvme_ctrlr *ctrlr)
{
/* Immediately mark the controller as ready for now */
ctrlr->state = NVME_CTRLR_STATE_READY;
return 0;
}
static void
free_ctrlr(struct nvme_ctrlr *ctrlr)
{
@ -372,7 +404,17 @@ probe_internal(struct spdk_pci_addr *addr, nvme_attach_cb attach_cb, void *cb_ct
return rc;
}
while (!TAILQ_EMPTY(&ctrlrs)) {
TAILQ_FOREACH_SAFE(ctrlr, &ctrlrs, tailq, tmp) {
rc = process_ctrlr_init(ctrlr);
if (rc != 0) {
SPDK_ERRLOG("NVMe controller initialization failed\n");
TAILQ_REMOVE(&ctrlrs, ctrlr, tailq);
free_ctrlr(ctrlr);
continue;
}
if (ctrlr->state == NVME_CTRLR_STATE_READY) {
TAILQ_REMOVE(&ctrlrs, ctrlr, tailq);
TAILQ_INSERT_TAIL(&g_nvme_ctrlrs, ctrlr, tailq);
@ -380,6 +422,8 @@ probe_internal(struct spdk_pci_addr *addr, nvme_attach_cb attach_cb, void *cb_ct
attach_cb(cb_ctx, &ctrlr->pci_device->addr, ctrlr);
}
}
}
}
return 0;
}