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idxd: clean up some enum style issues for consistency

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Signed-off-by: paul luse <paul.e.luse@intel.com>
Change-Id: I523176cc49951e6d6513b86b1e05ca8e2b5e62f5
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/2022
Community-CI: Mellanox Build Bot
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Aleksey Marchuk <alexeymar@mellanox.com>
Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com>
Reviewed-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
This commit is contained in:
paul luse 2020-04-24 11:04:25 -04:00 committed by Tomasz Zawadzki
parent 2755fbdf35
commit 9d94a8d53a
3 changed files with 106 additions and 106 deletions
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10
include/spdk_internal/accel_engine.h
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@ -40,11 +40,11 @@
#include "spdk/queue.h" #include "spdk/queue.h"
enum accel_module { enum accel_module {
ACCEL_SW = 0, ACCEL_SW = 0,
ACCEL_AUTO, ACCEL_AUTO = 1,
ACCEL_CBDMA, ACCEL_CBDMA = 2,
ACCEL_IDXD_DSA, ACCEL_IDXD_DSA = 3,
ACCEL_MODULE_MAX ACCEL_MODULE_MAX = 4,
}; };
int accel_set_module(enum accel_module *opts); int accel_set_module(enum accel_module *opts);

34
include/spdk_internal/idxd.h
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@ -48,23 +48,23 @@ extern "C" {
#define IDXD_MAX_CONFIG_NUM 1 #define IDXD_MAX_CONFIG_NUM 1
enum dsa_opcode { enum dsa_opcode {
IDXD_OPCODE_NOOP = 0, IDXD_OPCODE_NOOP = 0,
IDXD_OPCODE_BATCH = 1, IDXD_OPCODE_BATCH = 1,
IDXD_OPCODE_DRAIN = 2, IDXD_OPCODE_DRAIN = 2,
IDXD_OPCODE_MEMMOVE = 3, IDXD_OPCODE_MEMMOVE = 3,
IDXD_OPCODE_MEMFILL = 4, IDXD_OPCODE_MEMFILL = 4,
IDXD_OPCODE_COMPARE = 5, IDXD_OPCODE_COMPARE = 5,
IDXD_OPCODE_COMPVAL = 6, IDXD_OPCODE_COMPVAL = 6,
IDXD_OPCODE_CR_DELTA = 7, IDXD_OPCODE_CR_DELTA = 7,
IDXD_OPCODE_AP_DELTA = 8, IDXD_OPCODE_AP_DELTA = 8,
IDXD_OPCODE_DUALCAST = 9, IDXD_OPCODE_DUALCAST = 9,
IDXD_OPCODE_CRCGEN = 16, IDXD_OPCODE_CRCGEN = 16,
IDXD_OPCODE_COPY_CRC = 17, IDXD_OPCODE_COPY_CRC = 17,
IDXD_OPCODE_DIF_CHECK = 18, IDXD_OPCODE_DIF_CHECK = 18,
IDXD_OPCODE_DIF_INS = 19, IDXD_OPCODE_DIF_INS = 19,
IDXD_OPCODE_DIF_STRP = 20, IDXD_OPCODE_DIF_STRP = 20,
IDXD_OPCODE_DIF_UPDT = 21, IDXD_OPCODE_DIF_UPDT = 21,
IDXD_OPCODE_CFLUSH = 32, IDXD_OPCODE_CFLUSH = 32,
}; };
#ifdef __cplusplus #ifdef __cplusplus

168
lib/idxd/idxd_spec.h
View File

@ -84,114 +84,114 @@ extern "C" {
* supported one. * supported one.
*/ */
enum dsa_completion_status { enum dsa_completion_status {
IDXD_COMP_NONE = 0, IDXD_COMP_NONE = 0,
IDXD_COMP_SUCCESS = 1, IDXD_COMP_SUCCESS = 1,
IDXD_COMP_SUCCESS_PRED = 2, IDXD_COMP_SUCCESS_PRED = 2,
IDXD_COMP_PAGE_FAULT_NOBOF = 3, IDXD_COMP_PAGE_FAULT_NOBOF = 3,
IDXD_COMP_PAGE_FAULT_IR = 4, IDXD_COMP_PAGE_FAULT_IR = 4,
IDXD_COMP_BATCH_FAIL = 5, IDXD_COMP_BATCH_FAIL = 5,
IDXD_COMP_BATCH_PAGE_FAULT = 6, IDXD_COMP_BATCH_PAGE_FAULT = 6,
IDXD_COMP_DR_OFFSET_NOINC = 7, IDXD_COMP_DR_OFFSET_NOINC = 7,
IDXD_COMP_DR_OFFSET_ERANGE = 8, IDXD_COMP_DR_OFFSET_ERANGE = 8,
IDXD_COMP_DIF_ERR = 9, IDXD_COMP_DIF_ERR = 9,
IDXD_COMP_BAD_OPCODE = 16, IDXD_COMP_BAD_OPCODE = 16,
IDXD_COMP_INVALID_FLAGS = 17, IDXD_COMP_INVALID_FLAGS = 17,
IDXD_COMP_NOZERO_RESERVE = 18, IDXD_COMP_NOZERO_RESERVE = 18,
IDXD_COMP_XFER_ERANGE = 19, IDXD_COMP_XFER_ERANGE = 19,
IDXD_COMP_DESC_CNT_ERANGE = 20, IDXD_COMP_DESC_CNT_ERANGE = 20,
IDXD_COMP_DR_ERANGE = 21, IDXD_COMP_DR_ERANGE = 21,
IDXD_COMP_OVERLAP_BUFFERS = 22, IDXD_COMP_OVERLAP_BUFFERS = 22,
IDXD_COMP_DCAST_ERR = 23, IDXD_COMP_DCAST_ERR = 23,
IDXD_COMP_DESCLIST_ALIGN = 24, IDXD_COMP_DESCLIST_ALIGN = 24,
IDXD_COMP_INT_HANDLE_INVAL = 25, IDXD_COMP_INT_HANDLE_INVAL = 25,
IDXD_COMP_CRA_XLAT = 26, IDXD_COMP_CRA_XLAT = 26,
IDXD_COMP_CRA_ALIGN = 27, IDXD_COMP_CRA_ALIGN = 27,
IDXD_COMP_ADDR_ALIGN = 28, IDXD_COMP_ADDR_ALIGN = 28,
IDXD_COMP_PRIV_BAD = 29, IDXD_COMP_PRIV_BAD = 29,
IDXD_COMP_TRAFFIC_CLASS_CONF = 30, IDXD_COMP_TRAFFIC_CLASS_CONF = 30,
IDXD_COMP_PFAULT_RDBA = 31, IDXD_COMP_PFAULT_RDBA = 31,
IDXD_COMP_HW_ERR1 = 32, IDXD_COMP_HW_ERR1 = 32,
IDXD_COMP_HW_ERR_DRB = 33, IDXD_COMP_HW_ERR_DRB = 33,
IDXD_COMP_TRANSLATION_FAIL = 34, IDXD_COMP_TRANSLATION_FAIL = 34,
}; };
enum idxd_wq_state { enum idxd_wq_state {
WQ_DISABLED = 0, WQ_DISABLED = 0,
WQ_ENABLED = 1, WQ_ENABLED = 1,
}; };
enum idxd_wq_flag { enum idxd_wq_flag {
WQ_FLAG_DEDICATED = 0, WQ_FLAG_DEDICATED = 0,
WQ_FLAG_BOF = 1, WQ_FLAG_BOF = 1,
}; };
enum idxd_wq_type { enum idxd_wq_type {
WQT_NONE = 0, WQT_NONE = 0,
WQT_KERNEL = 1, WQT_KERNEL = 1,
WQT_USER = 2, WQT_USER = 2,
WQT_MDEV = 3, WQT_MDEV = 3,
}; };
enum idxd_dev_state { enum idxd_dev_state {
IDXD_DEVICE_STATE_DISABLED = 0, IDXD_DEVICE_STATE_DISABLED = 0,
IDXD_DEVICE_STATE_ENABLED = 1, IDXD_DEVICE_STATE_ENABLED = 1,
IDXD_DEVICE_STATE_DRAIN = 2, IDXD_DEVICE_STATE_DRAIN = 2,
IDXD_DEVICE_STATE_HALT = 3, IDXD_DEVICE_STATE_HALT = 3,
}; };
enum idxd_device_reset_type { enum idxd_device_reset_type {
IDXD_DEVICE_RESET_SOFTWARE = 0, IDXD_DEVICE_RESET_SOFTWARE = 0,
IDXD_DEVICE_RESET_FLR = 1, IDXD_DEVICE_RESET_FLR = 1,
IDXD_DEVICE_RESET_WARM = 2, IDXD_DEVICE_RESET_WARM = 2,
IDXD_DEVICE_RESET_COLD = 3, IDXD_DEVICE_RESET_COLD = 3,
}; };
enum idxd_cmds { enum idxd_cmds {
IDXD_ENABLE_DEV = 1, IDXD_ENABLE_DEV = 1,
IDXD_DISABLE_DEV = 2, IDXD_DISABLE_DEV = 2,
IDXD_DRAIN_ALL = 3, IDXD_DRAIN_ALL = 3,
IDXD_ABORT_ALL = 4, IDXD_ABORT_ALL = 4,
IDXD_RESET_DEVICE = 5, IDXD_RESET_DEVICE = 5,
IDXD_ENABLE_WQ = 6, IDXD_ENABLE_WQ = 6,
IDXD_DISABLE_WQ = 7, IDXD_DISABLE_WQ = 7,
IDXD_DRAIN_WQ = 8, IDXD_DRAIN_WQ = 8,
IDXD_ABORT_WQ = 9, IDXD_ABORT_WQ = 9,
IDXD_RESET_WQ = 10, IDXD_RESET_WQ = 10,
}; };
enum idxd_cmdsts_err { enum idxd_cmdsts_err {
IDXD_CMDSTS_SUCCESS = 0, IDXD_CMDSTS_SUCCESS = 0,
IDXD_CMDSTS_INVAL_CMD = 1, IDXD_CMDSTS_INVAL_CMD = 1,
IDXD_CMDSTS_INVAL_WQIDX = 2, IDXD_CMDSTS_INVAL_WQIDX = 2,
IDXD_CMDSTS_HW_ERR = 3, IDXD_CMDSTS_HW_ERR = 3,
IDXD_CMDSTS_ERR_DEV_ENABLED = 16, IDXD_CMDSTS_ERR_DEV_ENABLED = 16,
IDXD_CMDSTS_ERR_CONFIG = 17, IDXD_CMDSTS_ERR_CONFIG = 17,
IDXD_CMDSTS_ERR_BUSMASTER_EN = 18, IDXD_CMDSTS_ERR_BUSMASTER_EN = 18,
IDXD_CMDSTS_ERR_PASID_INVAL = 19, IDXD_CMDSTS_ERR_PASID_INVAL = 19,
IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE = 20, IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE = 20,
IDXD_CMDSTS_ERR_GRP_CONFIG = 21, IDXD_CMDSTS_ERR_GRP_CONFIG = 21,
IDXD_CMDSTS_ERR_GRP_CONFIG2 = 22, IDXD_CMDSTS_ERR_GRP_CONFIG2 = 22,
IDXD_CMDSTS_ERR_GRP_CONFIG3 = 23, IDXD_CMDSTS_ERR_GRP_CONFIG3 = 23,
IDXD_CMDSTS_ERR_GRP_CONFIG4 = 24, IDXD_CMDSTS_ERR_GRP_CONFIG4 = 24,
IDXD_CMDSTS_ERR_DEV_NOTEN = 32, IDXD_CMDSTS_ERR_DEV_NOTEN = 32,
IDXD_CMDSTS_ERR_WQ_ENABLED = 33, IDXD_CMDSTS_ERR_WQ_ENABLED = 33,
IDXD_CMDSTS_ERR_WQ_SIZE = 34, IDXD_CMDSTS_ERR_WQ_SIZE = 34,
IDXD_CMDSTS_ERR_WQ_PRIOR = 35, IDXD_CMDSTS_ERR_WQ_PRIOR = 35,
IDXD_CMDSTS_ERR_WQ_MODE = 36, IDXD_CMDSTS_ERR_WQ_MODE = 36,
IDXD_CMDSTS_ERR_BOF_EN = 37, IDXD_CMDSTS_ERR_BOF_EN = 37,
IDXD_CMDSTS_ERR_PASID_EN = 38, IDXD_CMDSTS_ERR_PASID_EN = 38,
IDXD_CMDSTS_ERR_MAX_BATCH_SIZE = 39, IDXD_CMDSTS_ERR_MAX_BATCH_SIZE = 39,
IDXD_CMDSTS_ERR_MAX_XFER_SIZE = 40, IDXD_CMDSTS_ERR_MAX_XFER_SIZE = 40,
IDXD_CMDSTS_ERR_DIS_DEV_EN = 49, IDXD_CMDSTS_ERR_DIS_DEV_EN = 49,
IDXD_CMDSTS_ERR_DEV_NOT_EN = 50, IDXD_CMDSTS_ERR_DEV_NOT_EN = 50,
IDXD_CMDSTS_ERR_INVAL_INT_IDX = 65, IDXD_CMDSTS_ERR_INVAL_INT_IDX = 65,
IDXD_CMDSTS_ERR_NO_HANDLE = 66, IDXD_CMDSTS_ERR_NO_HANDLE = 66,
}; };
enum idxd_wq_hw_state { enum idxd_wq_hw_state {
IDXD_WQ_DEV_DISABLED = 0, IDXD_WQ_DEV_DISABLED = 0,
IDXD_WQ_DEV_ENABLED = 1, IDXD_WQ_DEV_ENABLED = 1,
IDXD_WQ_DEV_BUSY = 2, IDXD_WQ_DEV_BUSY = 2,
}; };
struct idxd_hw_desc { struct idxd_hw_desc {