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nvme: simplify supported log page code

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Change-Id: If16b1c237dc304378fe0742651a78d3ec0850665
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
This commit is contained in:
Daniel Verkamp 2016-01-15 13:21:18 -07:00
parent ab17933468
commit 97601bb358
2 changed files with 16 additions and 62 deletions
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59
lib/nvme/nvme_ctrlr.c
View File

@ -45,28 +45,22 @@ static void
nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr, nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr,
struct nvme_intel_log_page_directory *log_page_directory) struct nvme_intel_log_page_directory *log_page_directory)
{ {
int i = 0;
if (ctrlr->cdata.vid != PCI_VENDOR_ID_INTEL || log_page_directory == NULL) if (ctrlr->cdata.vid != PCI_VENDOR_ID_INTEL || log_page_directory == NULL)
return; return;
ctrlr->supported_log_pages.vendor_specific_page_id[i] = NVME_INTEL_LOG_PAGE_DIRECTORY; ctrlr->log_page_supported[NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
i++;
if (log_page_directory->read_latency_log_len) { if (log_page_directory->read_latency_log_len) {
ctrlr->supported_log_pages.vendor_specific_page_id[i] = NVME_INTEL_LOG_READ_CMD_LATENCY; ctrlr->log_page_supported[NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
i++;
} }
if (log_page_directory->write_latency_log_len) { if (log_page_directory->write_latency_log_len) {
ctrlr->supported_log_pages.vendor_specific_page_id[i] = NVME_INTEL_LOG_WRITE_CMD_LATENCY; ctrlr->log_page_supported[NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
i++;
} }
if (log_page_directory->temperature_statistics_log_len) { if (log_page_directory->temperature_statistics_log_len) {
ctrlr->supported_log_pages.vendor_specific_page_id[i] = NVME_INTEL_LOG_TEMPERATURE; ctrlr->log_page_supported[NVME_INTEL_LOG_TEMPERATURE] = true;
i++;
} }
if (log_page_directory->smart_log_len) { if (log_page_directory->smart_log_len) {
ctrlr->supported_log_pages.vendor_specific_page_id[i] = NVME_INTEL_LOG_SMART; ctrlr->log_page_supported[NVME_INTEL_LOG_SMART] = true;
} }
} }
@ -106,15 +100,15 @@ static int nvme_ctrlr_set_intel_support_log_pages(struct nvme_controller *ctrlr)
static void static void
nvme_ctrlr_set_supported_log_pages(struct nvme_controller *ctrlr) nvme_ctrlr_set_supported_log_pages(struct nvme_controller *ctrlr)
{ {
memset(&ctrlr->supported_log_pages, 0, sizeof(struct nvme_supported_log_pages)); memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
ctrlr->supported_log_pages.vendor_id = ctrlr->cdata.vid; /* Mandatory pages */
ctrlr->supported_log_pages.generic_page_id[0] = NVME_LOG_ERROR; ctrlr->log_page_supported[NVME_LOG_ERROR] = true;
ctrlr->supported_log_pages.generic_page_id[1] = NVME_LOG_HEALTH_INFORMATION; ctrlr->log_page_supported[NVME_LOG_HEALTH_INFORMATION] = true;
ctrlr->supported_log_pages.generic_page_id[2] = NVME_LOG_FIRMWARE_SLOT; ctrlr->log_page_supported[NVME_LOG_FIRMWARE_SLOT] = true;
if (ctrlr->cdata.lpa.celp) { if (ctrlr->cdata.lpa.celp) {
ctrlr->supported_log_pages.generic_page_id[3] = NVME_LOG_COMMAND_EFFECTS_LOG; ctrlr->log_page_supported[NVME_LOG_COMMAND_EFFECTS_LOG] = true;
} }
if (ctrlr->supported_log_pages.vendor_id == PCI_VENDOR_ID_INTEL) { if (ctrlr->cdata.vid == PCI_VENDOR_ID_INTEL) {
nvme_ctrlr_set_intel_support_log_pages(ctrlr); nvme_ctrlr_set_intel_support_log_pages(ctrlr);
} }
} }
@ -865,30 +859,7 @@ nvme_ctrlr_register_aer_callback(struct nvme_controller *ctrlr,
bool bool
nvme_ctrlr_is_log_page_supported(struct nvme_controller *ctrlr, uint8_t log_page) nvme_ctrlr_is_log_page_supported(struct nvme_controller *ctrlr, uint8_t log_page)
{ {
unsigned int i = 0; /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
while (i < sizeof(ctrlr->supported_log_pages.generic_page_id)) { return ctrlr->log_page_supported[log_page];
if (log_page == ctrlr->supported_log_pages.generic_page_id[i]) {
return true;
}
i++;
}
i = 0;
while (i < sizeof(ctrlr->supported_log_pages.command_set_page_id)) {
if (log_page == ctrlr->supported_log_pages.command_set_page_id[i]) {
return true;
}
i++;
}
i = 0;
while (i < sizeof(ctrlr->supported_log_pages.vendor_specific_page_id)) {
if (log_page == ctrlr->supported_log_pages.vendor_specific_page_id[i]) {
return true;
}
i++;
}
return false;
} }

19
lib/nvme/nvme_internal.h
View File

@ -232,23 +232,6 @@ struct nvme_namespace {
uint16_t flags; uint16_t flags;
}; };
/** \brief supported log pages. */
struct nvme_supported_log_pages {
uint32_t vendor_id;
/**
* List of supported generic log page IDs, terminated with 0.
*/
uint8_t generic_page_id[128];
/**
* List of supported command set page IDs, terminated with 0.
*/
uint8_t command_set_page_id[64];
/**
* List of supported vendor specific page IDs, terminated with 0.
*/
uint8_t vendor_specific_page_id[64];
};
/* /*
* One of these per allocated PCI device. * One of these per allocated PCI device.
*/ */
@ -273,7 +256,7 @@ struct nvme_controller {
/* Cold data (not accessed in normal I/O path) is after this point. */ /* Cold data (not accessed in normal I/O path) is after this point. */
/** All the log pages supported */ /** All the log pages supported */
struct nvme_supported_log_pages supported_log_pages; bool log_page_supported[256];
/* Opaque handle to associated PCI device. */ /* Opaque handle to associated PCI device. */
void *devhandle; void *devhandle;