From 8cb09df68e0166cfcc26e35973069c84eabc019f Mon Sep 17 00:00:00 2001 From: Daniel Verkamp Date: Mon, 8 Feb 2016 14:08:06 -0700 Subject: [PATCH] pci_ids: add SPDK_ prefix PCI_VENDOR_ID_INTEL -> SPDK_PCI_VID_INTEL Also change the inclusion guard macro to be consistent with the other SPDK headers. Change-Id: I29346267172cb8c07cc4289eed4eca2d55e942d6 Signed-off-by: Daniel Verkamp --- examples/nvme/identify/identify.c | 2 +- include/spdk/pci_ids.h | 8 ++++---- lib/ioat/ioat_impl.h | 2 +- lib/nvme/nvme_ctrlr.c | 6 +++--- lib/nvme/nvme_intel.c | 12 ++++++------ test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c | 10 +++++----- 6 files changed, 20 insertions(+), 20 deletions(-) diff --git a/examples/nvme/identify/identify.c b/examples/nvme/identify/identify.c index dcdbd6f7d..8b7c58ee7 100644 --- a/examples/nvme/identify/identify.c +++ b/examples/nvme/identify/identify.c @@ -243,7 +243,7 @@ get_log_pages(struct nvme_controller *ctrlr) } ctrlr_data = nvme_ctrlr_get_data(ctrlr); - if (ctrlr_data->vid == PCI_VENDOR_ID_INTEL) { + if (ctrlr_data->vid == SPDK_PCI_VID_INTEL) { if (nvme_ctrlr_is_log_page_supported(ctrlr, NVME_INTEL_LOG_SMART)) { if (get_intel_smart_log_page(ctrlr) == 0) { outstanding_commands++; diff --git a/include/spdk/pci_ids.h b/include/spdk/pci_ids.h index ccbd5bb01..999319f1a 100644 --- a/include/spdk/pci_ids.h +++ b/include/spdk/pci_ids.h @@ -31,11 +31,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __PCI_IDS_H__ -#define __PCI_IDS_H__ +#ifndef SPDK_PCI_IDS +#define SPDK_PCI_IDS #include -#define PCI_VENDOR_ID_INTEL 0x8086 +#define SPDK_PCI_VID_INTEL 0x8086 -#endif /* __PCI_IDS_H__ */ +#endif /* SPDK_PCI_IDS */ diff --git a/lib/ioat/ioat_impl.h b/lib/ioat/ioat_impl.h index 49b850298..084613c31 100644 --- a/lib/ioat/ioat_impl.h +++ b/lib/ioat/ioat_impl.h @@ -81,7 +81,7 @@ ioat_zmalloc(const char *tag, size_t size, unsigned align, uint64_t *phys_addr) static inline bool ioat_pci_device_match_id(uint16_t vendor_id, uint16_t device_id) { - if (vendor_id != PCI_VENDOR_ID_INTEL) { + if (vendor_id != SPDK_PCI_VID_INTEL) { return false; } diff --git a/lib/nvme/nvme_ctrlr.c b/lib/nvme/nvme_ctrlr.c index 2e8461e07..0da0b0129 100644 --- a/lib/nvme/nvme_ctrlr.c +++ b/lib/nvme/nvme_ctrlr.c @@ -49,7 +49,7 @@ nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr, struct spdk_pci_device *dev; struct pci_id pci_id; - if (ctrlr->cdata.vid != PCI_VENDOR_ID_INTEL || log_page_directory == NULL) + if (ctrlr->cdata.vid != SPDK_PCI_VID_INTEL || log_page_directory == NULL) return; dev = ctrlr->devhandle; @@ -120,7 +120,7 @@ nvme_ctrlr_set_supported_log_pages(struct nvme_controller *ctrlr) if (ctrlr->cdata.lpa.celp) { ctrlr->log_page_supported[NVME_LOG_COMMAND_EFFECTS_LOG] = true; } - if (ctrlr->cdata.vid == PCI_VENDOR_ID_INTEL) { + if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) { nvme_ctrlr_set_intel_support_log_pages(ctrlr); } } @@ -161,7 +161,7 @@ nvme_ctrlr_set_supported_features(struct nvme_controller *ctrlr) if (ctrlr->cdata.hmpre) { ctrlr->feature_supported[NVME_FEAT_HOST_MEM_BUFFER] = true; } - if (ctrlr->cdata.vid == PCI_VENDOR_ID_INTEL) { + if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) { nvme_ctrlr_set_intel_supported_features(ctrlr); } } diff --git a/lib/nvme/nvme_intel.c b/lib/nvme/nvme_intel.c index 3f17b4253..0cb433754 100644 --- a/lib/nvme/nvme_intel.c +++ b/lib/nvme/nvme_intel.c @@ -42,12 +42,12 @@ struct nvme_intel_quirk { }; static const struct nvme_intel_quirk intel_p3x00[] = { - {{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, - {{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, - {{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, - {{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, - {{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, - {{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, + {{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, + {{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, + {{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, + {{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, + {{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, + {{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY }, {{0x0000, 0x0000, 0x0000, 0x0000}, 0 } }; diff --git a/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c b/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c index 065ba4f10..eb9e8d7a1 100644 --- a/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c +++ b/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c @@ -239,7 +239,7 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void) CU_ASSERT(res == false); /* set valid vendor id and log page directory*/ - ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL; + ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; payload.temperature_statistics_log_len = 1; memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); @@ -254,11 +254,11 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void) CU_ASSERT(res == false); /* set valid vendor id, device id and sub device id*/ - ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL; + ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; payload.temperature_statistics_log_len = 0; - g_pci_vendor_id = PCI_VENDOR_ID_INTEL; + g_pci_vendor_id = SPDK_PCI_VID_INTEL; g_pci_device_id = 0x0953; - g_pci_subvendor_id = PCI_VENDOR_ID_INTEL; + g_pci_subvendor_id = SPDK_PCI_VID_INTEL; g_pci_subdevice_id = 0x3702; memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); @@ -287,7 +287,7 @@ test_nvme_ctrlr_set_supported_features(void) res = nvme_ctrlr_is_feature_supported(&ctrlr, NVME_INTEL_FEAT_MAX_LBA); CU_ASSERT(res == false); - ctrlr.cdata.vid = PCI_VENDOR_ID_INTEL; + ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; nvme_ctrlr_set_supported_features(&ctrlr); res = nvme_ctrlr_is_feature_supported(&ctrlr, NVME_FEAT_ARBITRATION); CU_ASSERT(res == true);