nvme/pcie: Add support for Persistent Memory Region (PMR)
Implemented functions to enable, disable, map and unmap the PMR. Signed-off-by: Krishna Kanth Reddy <krish.reddy@samsung.com> Change-Id: I580e0b5060cefe1230c3db1361aee1957db457b2 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6559 Community-CI: Broadcom CI Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com>
This commit is contained in:
Krishna Kanth Reddy
Jim Harris
parent
8d506e8056
commit
89858bbf5d
@ -63,6 +63,8 @@ chained accelerated CRC32 computation support.
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### nvme
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Added NVMe transport operations to enable, disable, map and unmap the PMR.
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Added `spdk_nvme_qpair_get_optimal_poll_group` function and `qpair_get_optimal_poll_group`
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function pointer in spdk_nvmf_transport_ops structure in order to add the qpair to the most
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suitable polling group.
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@ -3537,6 +3537,14 @@ struct spdk_nvme_transport_ops {
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int (*ctrlr_unmap_cmb)(struct spdk_nvme_ctrlr *ctrlr);
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int (*ctrlr_enable_pmr)(struct spdk_nvme_ctrlr *ctrlr);
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int (*ctrlr_disable_pmr)(struct spdk_nvme_ctrlr *ctrlr);
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void *(*ctrlr_map_pmr)(struct spdk_nvme_ctrlr *ctrlr, size_t *size);
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int (*ctrlr_unmap_pmr)(struct spdk_nvme_ctrlr *ctrlr);
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struct spdk_nvme_qpair *(*ctrlr_create_io_qpair)(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid,
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const struct spdk_nvme_io_qpair_opts *opts);
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@ -865,6 +865,9 @@ struct spdk_nvme_ctrlr {
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uint32_t max_zone_append_size;
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STAILQ_HEAD(, spdk_nvme_ctrlr_aer_completion_list) async_events;
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/* PMR size in bytes */
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uint64_t pmr_size;
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};
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struct spdk_nvme_probe_ctx {
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@ -1315,6 +1318,10 @@ struct spdk_nvme_qpair *nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ct
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int nvme_transport_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr);
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void *nvme_transport_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size);
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int nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr);
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int nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr);
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int nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr);
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void *nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size);
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int nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr);
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int nvme_transport_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
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struct spdk_nvme_qpair *qpair);
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int nvme_transport_ctrlr_connect_qpair(struct spdk_nvme_ctrlr *ctrlr,
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@ -271,7 +271,49 @@ nvme_pcie_ctrlr_get_cmbsz(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_cmbsz_
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&cmbsz->raw);
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}
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static uint32_t
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static int
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nvme_pcie_ctrlr_get_pmrcap(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_pmrcap_register *pmrcap)
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{
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return nvme_pcie_ctrlr_get_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
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&pmrcap->raw);
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}
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static int
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nvme_pcie_ctrlr_set_pmrctl(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_pmrctl_register *pmrctl)
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{
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return nvme_pcie_ctrlr_set_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, pmrctl.raw),
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pmrctl->raw);
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}
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static int
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nvme_pcie_ctrlr_get_pmrctl(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_pmrctl_register *pmrctl)
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{
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return nvme_pcie_ctrlr_get_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, pmrctl.raw),
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&pmrctl->raw);
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}
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static int
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nvme_pcie_ctrlr_get_pmrsts(struct nvme_pcie_ctrlr *pctrlr, union spdk_nvme_pmrsts_register *pmrsts)
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{
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return nvme_pcie_ctrlr_get_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, pmrsts.raw),
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&pmrsts->raw);
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}
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static int
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nvme_pcie_ctrlr_set_pmrmscl(struct nvme_pcie_ctrlr *pctrlr, uint32_t value)
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{
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return nvme_pcie_ctrlr_set_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, pmrmscl.raw),
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value);
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}
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static int
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nvme_pcie_ctrlr_set_pmrmscu(struct nvme_pcie_ctrlr *pctrlr, uint32_t value)
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{
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return nvme_pcie_ctrlr_set_reg_4(&pctrlr->ctrlr, offsetof(struct spdk_nvme_registers, pmrmscu),
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value);
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}
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static uint32_t
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nvme_pcie_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr)
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{
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/*
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@ -475,6 +517,272 @@ nvme_pcie_ctrlr_unmap_io_cmb(struct spdk_nvme_ctrlr *ctrlr)
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return rc;
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}
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static void
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nvme_pcie_ctrlr_map_pmr(struct nvme_pcie_ctrlr *pctrlr)
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{
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int rc;
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void *addr = NULL;
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uint32_t bir;
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union spdk_nvme_pmrcap_register pmrcap;
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uint64_t bar_size = 0, bar_phys_addr = 0;
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if (!pctrlr->regs->cap.bits.pmrs) {
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return;
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}
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if (nvme_pcie_ctrlr_get_pmrcap(pctrlr, &pmrcap)) {
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SPDK_ERRLOG("get registers failed\n");
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return;
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}
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bir = pmrcap.bits.bir;
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/* Values 2 3 4 5 are valid for BAR */
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if (bir > 5 || bir < 2) {
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SPDK_ERRLOG("invalid base indicator register value\n");
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return;
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}
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rc = spdk_pci_device_map_bar(pctrlr->devhandle, bir, &addr, &bar_phys_addr, &bar_size);
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if ((rc != 0) || addr == NULL) {
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SPDK_ERRLOG("could not map the bar %d\n", bir);
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return;
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}
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if (pmrcap.bits.cmss) {
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uint32_t pmrmscl, pmrmscu, cmse = 1;
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union spdk_nvme_pmrsts_register pmrsts;
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/* Enable Controller Memory Space */
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pmrmscl = (uint32_t)((bar_phys_addr & 0xFFFFF000ULL) | (cmse << 1));
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pmrmscu = (uint32_t)((bar_phys_addr >> 32ULL) & 0xFFFFFFFFULL);
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if (nvme_pcie_ctrlr_set_pmrmscu(pctrlr, pmrmscu)) {
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SPDK_ERRLOG("set_pmrmscu() failed\n");
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spdk_pci_device_unmap_bar(pctrlr->devhandle, bir, addr);
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return;
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}
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if (nvme_pcie_ctrlr_set_pmrmscl(pctrlr, pmrmscl)) {
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SPDK_ERRLOG("set_pmrmscl() failed\n");
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spdk_pci_device_unmap_bar(pctrlr->devhandle, bir, addr);
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return;
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}
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if (nvme_pcie_ctrlr_get_pmrsts(pctrlr, &pmrsts)) {
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SPDK_ERRLOG("get pmrsts failed\n");
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spdk_pci_device_unmap_bar(pctrlr->devhandle, bir, addr);
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return;
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}
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if (pmrsts.bits.cbai) {
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SPDK_ERRLOG("Controller Memory Space Enable Failure\n");
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SPDK_ERRLOG("CBA Invalid - Host Addresses cannot reference PMR\n");
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} else {
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SPDK_DEBUGLOG(nvme, "Controller Memory Space Enable Success\n");
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SPDK_DEBUGLOG(nvme, "Host Addresses can reference PMR\n");
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}
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}
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pctrlr->pmr.bar_va = addr;
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pctrlr->pmr.bar_pa = bar_phys_addr;
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pctrlr->pmr.size = pctrlr->ctrlr.pmr_size = bar_size;
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}
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static int
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nvme_pcie_ctrlr_unmap_pmr(struct nvme_pcie_ctrlr *pctrlr)
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{
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int rc = 0;
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union spdk_nvme_pmrcap_register pmrcap;
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void *addr = pctrlr->pmr.bar_va;
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if (addr == NULL) {
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return rc;
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}
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if (pctrlr->pmr.mem_register_addr) {
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spdk_mem_unregister(pctrlr->pmr.mem_register_addr, pctrlr->pmr.mem_register_size);
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}
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if (nvme_pcie_ctrlr_get_pmrcap(pctrlr, &pmrcap)) {
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SPDK_ERRLOG("get_pmrcap() failed\n");
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return -EIO;
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}
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if (pmrcap.bits.cmss) {
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if (nvme_pcie_ctrlr_set_pmrmscu(pctrlr, 0)) {
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SPDK_ERRLOG("set_pmrmscu() failed\n");
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}
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if (nvme_pcie_ctrlr_set_pmrmscl(pctrlr, 0)) {
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SPDK_ERRLOG("set_pmrmscl() failed\n");
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}
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}
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rc = spdk_pci_device_unmap_bar(pctrlr->devhandle, pmrcap.bits.bir, addr);
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return rc;
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}
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static int
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nvme_pcie_ctrlr_config_pmr(struct spdk_nvme_ctrlr *ctrlr, bool enable)
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{
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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union spdk_nvme_pmrcap_register pmrcap;
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union spdk_nvme_pmrctl_register pmrctl;
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union spdk_nvme_pmrsts_register pmrsts;
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uint8_t pmrto, pmrtu;
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uint64_t timeout_in_ms, ticks_per_ms, timeout_in_ticks, now_ticks;
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if (!pctrlr->regs->cap.bits.pmrs) {
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SPDK_ERRLOG("PMR is not supported by the controller\n");
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return -ENOTSUP;
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}
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if (nvme_pcie_ctrlr_get_pmrcap(pctrlr, &pmrcap)) {
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SPDK_ERRLOG("get registers failed\n");
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return -EIO;
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}
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pmrto = pmrcap.bits.pmrto;
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pmrtu = pmrcap.bits.pmrtu;
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if (pmrtu > 1) {
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SPDK_ERRLOG("PMR Time Units Invalid\n");
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return -EINVAL;
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}
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ticks_per_ms = spdk_get_ticks_hz() / 1000;
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timeout_in_ms = pmrto * (pmrtu ? (60 * 1000) : 500);
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timeout_in_ticks = timeout_in_ms * ticks_per_ms;
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if (nvme_pcie_ctrlr_get_pmrctl(pctrlr, &pmrctl)) {
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SPDK_ERRLOG("get pmrctl failed\n");
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return -EIO;
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}
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if (enable && pmrctl.bits.en != 0) {
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SPDK_ERRLOG("PMR is already enabled\n");
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return -EINVAL;
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} else if (!enable && pmrctl.bits.en != 1) {
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SPDK_ERRLOG("PMR is already disabled\n");
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return -EINVAL;
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}
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pmrctl.bits.en = enable;
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if (nvme_pcie_ctrlr_set_pmrctl(pctrlr, &pmrctl)) {
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SPDK_ERRLOG("set pmrctl failed\n");
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return -EIO;
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}
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now_ticks = spdk_get_ticks();
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do {
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if (nvme_pcie_ctrlr_get_pmrsts(pctrlr, &pmrsts)) {
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SPDK_ERRLOG("get pmrsts failed\n");
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return -EIO;
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}
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if (pmrsts.bits.nrdy == enable &&
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spdk_get_ticks() > now_ticks + timeout_in_ticks) {
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SPDK_ERRLOG("PMR Enable - Timed Out\n");
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return -ETIMEDOUT;
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}
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} while (pmrsts.bits.nrdy == enable);
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SPDK_DEBUGLOG(nvme, "PMR %s\n", enable ? "Enabled" : "Disabled");
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return 0;
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}
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static int
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nvme_pcie_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
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{
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return nvme_pcie_ctrlr_config_pmr(ctrlr, true);
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}
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static int
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nvme_pcie_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
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{
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return nvme_pcie_ctrlr_config_pmr(ctrlr, false);
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}
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static void *
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nvme_pcie_ctrlr_map_io_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
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{
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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union spdk_nvme_pmrcap_register pmrcap;
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uint64_t mem_register_start, mem_register_end;
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int rc;
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if (!pctrlr->regs->cap.bits.pmrs) {
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SPDK_ERRLOG("PMR is not supported by the controller\n");
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return NULL;
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}
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if (pctrlr->pmr.mem_register_addr != NULL) {
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*size = pctrlr->pmr.mem_register_size;
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return pctrlr->pmr.mem_register_addr;
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}
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*size = 0;
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if (pctrlr->pmr.bar_va == NULL) {
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SPDK_DEBUGLOG(nvme, "PMR not available\n");
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return NULL;
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}
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if (nvme_pcie_ctrlr_get_pmrcap(pctrlr, &pmrcap)) {
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SPDK_ERRLOG("get registers failed\n");
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return NULL;
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}
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/* Check if WDS / RDS is supported */
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if (!(pmrcap.bits.wds || pmrcap.bits.rds)) {
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return NULL;
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}
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/* If PMR is less than 4MiB in size then abort PMR mapping */
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if (pctrlr->pmr.size < (1ULL << 22)) {
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return NULL;
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}
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mem_register_start = _2MB_PAGE((uintptr_t)pctrlr->pmr.bar_va + VALUE_2MB - 1);
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mem_register_end = _2MB_PAGE((uintptr_t)pctrlr->pmr.bar_va + pctrlr->pmr.size);
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rc = spdk_mem_register((void *)mem_register_start, mem_register_end - mem_register_start);
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if (rc) {
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SPDK_ERRLOG("spdk_mem_register() failed\n");
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return NULL;
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}
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pctrlr->pmr.mem_register_addr = (void *)mem_register_start;
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pctrlr->pmr.mem_register_size = mem_register_end - mem_register_start;
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*size = pctrlr->pmr.mem_register_size;
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return pctrlr->pmr.mem_register_addr;
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}
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static int
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nvme_pcie_ctrlr_unmap_io_pmr(struct spdk_nvme_ctrlr *ctrlr)
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{
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struct nvme_pcie_ctrlr *pctrlr = nvme_pcie_ctrlr(ctrlr);
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int rc;
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if (pctrlr->pmr.mem_register_addr == NULL) {
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return -ENXIO;
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}
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rc = spdk_mem_unregister(pctrlr->pmr.mem_register_addr, pctrlr->pmr.mem_register_size);
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if (rc == 0) {
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pctrlr->pmr.mem_register_addr = NULL;
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pctrlr->pmr.mem_register_size = 0;
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}
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return rc;
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}
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static int
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nvme_pcie_ctrlr_allocate_bars(struct nvme_pcie_ctrlr *pctrlr)
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{
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@ -495,6 +803,7 @@ nvme_pcie_ctrlr_allocate_bars(struct nvme_pcie_ctrlr *pctrlr)
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pctrlr->regs_size = size;
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pctrlr->doorbell_base = (volatile uint32_t *)&pctrlr->regs->doorbell[0].sq_tdbl;
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nvme_pcie_ctrlr_map_cmb(pctrlr);
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nvme_pcie_ctrlr_map_pmr(pctrlr);
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return 0;
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}
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@ -509,6 +818,12 @@ nvme_pcie_ctrlr_free_bars(struct nvme_pcie_ctrlr *pctrlr)
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return rc;
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}
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rc = nvme_pcie_ctrlr_unmap_pmr(pctrlr);
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if (rc != 0) {
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SPDK_ERRLOG("nvme_ctrlr_unmap_pmr failed with error code %d\n", rc);
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return -1;
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}
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rc = nvme_pcie_ctrlr_unmap_cmb(pctrlr);
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if (rc != 0) {
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SPDK_ERRLOG("nvme_ctrlr_unmap_cmb failed with error code %d\n", rc);
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@ -1349,6 +1664,11 @@ const struct spdk_nvme_transport_ops pcie_ops = {
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.ctrlr_map_cmb = nvme_pcie_ctrlr_map_io_cmb,
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.ctrlr_unmap_cmb = nvme_pcie_ctrlr_unmap_io_cmb,
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.ctrlr_enable_pmr = nvme_pcie_ctrlr_enable_pmr,
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.ctrlr_disable_pmr = nvme_pcie_ctrlr_disable_pmr,
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.ctrlr_map_pmr = nvme_pcie_ctrlr_map_io_pmr,
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.ctrlr_unmap_pmr = nvme_pcie_ctrlr_unmap_io_pmr,
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|
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.ctrlr_create_io_qpair = nvme_pcie_ctrlr_create_io_qpair,
|
||||
.ctrlr_delete_io_qpair = nvme_pcie_ctrlr_delete_io_qpair,
|
||||
.ctrlr_connect_qpair = nvme_pcie_ctrlr_connect_qpair,
|
||||
|
||||
@ -76,6 +76,20 @@ struct nvme_pcie_ctrlr {
|
||||
size_t mem_register_size;
|
||||
} cmb;
|
||||
|
||||
struct {
|
||||
/* BAR mapping address which contains persistent memory region */
|
||||
void *bar_va;
|
||||
|
||||
/* BAR physical address which contains persistent memory region */
|
||||
uint64_t bar_pa;
|
||||
|
||||
/* Persistent memory region size in Bytes */
|
||||
uint64_t size;
|
||||
|
||||
void *mem_register_addr;
|
||||
size_t mem_register_size;
|
||||
} pmr;
|
||||
|
||||
/** stride in uint32_t units between doorbell registers (1 = 4 bytes, 2 = 8 bytes, ...) */
|
||||
uint32_t doorbell_stride_u32;
|
||||
|
||||
|
||||
@ -260,6 +260,58 @@ nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
|
||||
{
|
||||
const struct spdk_nvme_transport *transport = nvme_get_transport(ctrlr->trid.trstring);
|
||||
|
||||
assert(transport != NULL);
|
||||
if (transport->ops.ctrlr_enable_pmr != NULL) {
|
||||
return transport->ops.ctrlr_enable_pmr(ctrlr);
|
||||
}
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int
|
||||
nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
|
||||
{
|
||||
const struct spdk_nvme_transport *transport = nvme_get_transport(ctrlr->trid.trstring);
|
||||
|
||||
assert(transport != NULL);
|
||||
if (transport->ops.ctrlr_disable_pmr != NULL) {
|
||||
return transport->ops.ctrlr_disable_pmr(ctrlr);
|
||||
}
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
void *
|
||||
nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
|
||||
{
|
||||
const struct spdk_nvme_transport *transport = nvme_get_transport(ctrlr->trid.trstring);
|
||||
|
||||
assert(transport != NULL);
|
||||
if (transport->ops.ctrlr_map_pmr != NULL) {
|
||||
return transport->ops.ctrlr_map_pmr(ctrlr, size);
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int
|
||||
nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
|
||||
{
|
||||
const struct spdk_nvme_transport *transport = nvme_get_transport(ctrlr->trid.trstring);
|
||||
|
||||
assert(transport != NULL);
|
||||
if (transport->ops.ctrlr_unmap_pmr != NULL) {
|
||||
return transport->ops.ctrlr_unmap_pmr(ctrlr);
|
||||
}
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
struct spdk_nvme_qpair *
|
||||
nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid,
|
||||
const struct spdk_nvme_io_qpair_opts *opts)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user