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nvme: move devhandle from spdk_nvme_ctrlr to nvme_pcie_ctrlr

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This variable is only for nvme_pcie

Change-Id: I2bb8e65c3e6c26ef5919915b95d006bc92ebe750
Signed-off-by: Ziye Yang <ziye.yang@intel.com>
This commit is contained in:
Ziye Yang 2016-11-29 15:26:22 +08:00 committed by Daniel Verkamp
parent 7a17d4e249
commit 88ae5a7629
2 changed files with 8 additions and 8 deletions
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3
lib/nvme/nvme_internal.h
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@ -366,9 +366,6 @@ struct spdk_nvme_ctrlr {
/** All the features supported */ /** All the features supported */
bool feature_supported[256]; bool feature_supported[256];
/* Opaque handle to associated PCI device. */
struct spdk_pci_device *devhandle;
/** maximum i/o size in bytes */ /** maximum i/o size in bytes */
uint32_t max_xfer_size; uint32_t max_xfer_size;

13
lib/nvme/nvme_pcie.c
View File

@ -94,6 +94,9 @@ struct nvme_pcie_ctrlr {
/** stride in uint32_t units between doorbell registers (1 = 4 bytes, 2 = 8 bytes, ...) */ /** stride in uint32_t units between doorbell registers (1 = 4 bytes, 2 = 8 bytes, ...) */
uint32_t doorbell_stride_u32; uint32_t doorbell_stride_u32;
/* Opaque handle to associated PCI device. */
struct spdk_pci_device *devhandle;
}; };
struct nvme_tracker { struct nvme_tracker {
@ -306,7 +309,7 @@ nvme_pcie_ctrlr_map_cmb(struct nvme_pcie_ctrlr *pctrlr)
/* controller memory buffer offset from BAR in Bytes */ /* controller memory buffer offset from BAR in Bytes */
offset = unit_size * cmbloc.bits.ofst; offset = unit_size * cmbloc.bits.ofst;
rc = spdk_pci_device_map_bar(pctrlr->ctrlr.devhandle, bir, &addr, rc = spdk_pci_device_map_bar(pctrlr->devhandle, bir, &addr,
&bar_phys_addr, &bar_size); &bar_phys_addr, &bar_size);
if ((rc != 0) || addr == NULL) { if ((rc != 0) || addr == NULL) {
goto exit; goto exit;
@ -348,7 +351,7 @@ nvme_pcie_ctrlr_unmap_cmb(struct nvme_pcie_ctrlr *pctrlr)
SPDK_ERRLOG("get_cmbloc() failed\n"); SPDK_ERRLOG("get_cmbloc() failed\n");
return -EIO; return -EIO;
} }
rc = spdk_pci_device_unmap_bar(pctrlr->ctrlr.devhandle, cmbloc.bits.bir, addr); rc = spdk_pci_device_unmap_bar(pctrlr->devhandle, cmbloc.bits.bir, addr);
} }
return rc; return rc;
} }
@ -379,7 +382,7 @@ nvme_pcie_ctrlr_allocate_bars(struct nvme_pcie_ctrlr *pctrlr)
void *addr; void *addr;
uint64_t phys_addr, size; uint64_t phys_addr, size;
rc = spdk_pci_device_map_bar(pctrlr->ctrlr.devhandle, 0, &addr, rc = spdk_pci_device_map_bar(pctrlr->devhandle, 0, &addr,
&phys_addr, &size); &phys_addr, &size);
pctrlr->regs = (volatile struct spdk_nvme_registers *)addr; pctrlr->regs = (volatile struct spdk_nvme_registers *)addr;
if ((pctrlr->regs == NULL) || (rc != 0)) { if ((pctrlr->regs == NULL) || (rc != 0)) {
@ -406,7 +409,7 @@ nvme_pcie_ctrlr_free_bars(struct nvme_pcie_ctrlr *pctrlr)
} }
if (addr) { if (addr) {
rc = spdk_pci_device_unmap_bar(pctrlr->ctrlr.devhandle, 0, addr); rc = spdk_pci_device_unmap_bar(pctrlr->devhandle, 0, addr);
} }
return rc; return rc;
} }
@ -484,7 +487,7 @@ struct spdk_nvme_ctrlr *nvme_pcie_ctrlr_construct(enum spdk_nvme_transport trans
} }
pctrlr->ctrlr.transport = SPDK_NVME_TRANSPORT_PCIE; pctrlr->ctrlr.transport = SPDK_NVME_TRANSPORT_PCIE;
pctrlr->ctrlr.devhandle = devhandle; pctrlr->devhandle = devhandle;
rc = nvme_pcie_ctrlr_allocate_bars(pctrlr); rc = nvme_pcie_ctrlr_allocate_bars(pctrlr);
if (rc != 0) { if (rc != 0) {