test/llvm_nvme_fuzz: add SET FEATURES and GET FEATURES command test cases
Change-Id: I86464ab495d5ec984abcf795632c1c30c2c104d0 Signed-off-by: Yifan Bian <yifan.bian@intel.com> Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/11067 Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Dong Yi <dongx.yi@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com>
This commit is contained in:
Yifan Bian
Tomasz Zawadzki
parent
855390a585
commit
88a064de88
@ -293,6 +293,233 @@ fuzz_admin_directive_receive_command(struct fuzz_command *cmd)
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g_data += 8;
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g_data += 8;
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}
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}
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static void feat_arbitration(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_arbitration.bits.hpw = g_data[2];
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cmd->cmd.cdw11_bits.feat_arbitration.bits.mpw = g_data[3];
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cmd->cmd.cdw11_bits.feat_arbitration.bits.lpw = g_data[4];
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cmd->cmd.cdw11_bits.feat_arbitration.bits.ab = g_data[5] & 0x07;
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}
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static void feat_power_management(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_power_management.bits.wh = g_data[2] & 0x07;
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cmd->cmd.cdw11_bits.feat_power_management.bits.ps = (g_data[2] >> 3) & 0x1f;
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}
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static void feat_lba_range_type(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_lba_range_type.bits.num = (g_data[2] >> 2) & 0x3f;
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}
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static void feat_temperature_threshold(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_temp_threshold.bits.thsel = g_data[2] & 0x03;
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cmd->cmd.cdw11_bits.feat_temp_threshold.bits.tmpsel = (g_data[2] >> 2) & 0x0f;
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cmd->cmd.cdw11_bits.feat_temp_threshold.bits.tmpth = (g_data[3] << 8) + g_data[4];
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}
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static void feat_error_recover(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_error_recovery.bits.dulbe = g_data[2] & 0x01;
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cmd->cmd.cdw11_bits.feat_error_recovery.bits.tler = (g_data[3] << 8) + g_data[4];
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}
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static void feat_volatile_write_cache(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_volatile_write_cache.bits.wce = g_data[2] & 0x01;
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}
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static void feat_number_of_queues(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_num_of_queues.bits.ncqr = (g_data[2] << 8) + g_data[3];
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cmd->cmd.cdw11_bits.feat_num_of_queues.bits.nsqr = (g_data[4] << 8) + g_data[5];
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}
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static void feat_interrupt_coalescing(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_interrupt_coalescing.bits.time = g_data[2];
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cmd->cmd.cdw11_bits.feat_interrupt_coalescing.bits.thr = g_data[3];
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}
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static void feat_interrupt_vector_configuration(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_interrupt_vector_configuration.bits.cd = g_data[2] & 0x01;
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cmd->cmd.cdw11_bits.feat_interrupt_vector_configuration.bits.iv = (g_data[3] << 8) + g_data[4];
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}
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static void feat_write_atomicity(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_write_atomicity.bits.dn = g_data[2] & 0x01;
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}
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static void feat_async_event_cfg(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.ana_change_notice = g_data[2] & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.discovery_log_change_notice = (g_data[2] >> 1) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.fw_activation_notice = (g_data[2] >> 2) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.ns_attr_notice = (g_data[2] >> 3) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.telemetry_log_notice = (g_data[2] >> 4) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.crit_warn.bits.available_spare = g_data[3] & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.crit_warn.bits.device_reliability =
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(g_data[3] >> 1) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.crit_warn.bits.read_only = (g_data[3] >> 2) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.crit_warn.bits.temperature = (g_data[3] >> 3) & 0x01;
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cmd->cmd.cdw11_bits.feat_async_event_cfg.bits.crit_warn.bits.volatile_memory_backup =
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(g_data[3] >> 4) & 0x01;
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}
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static void feat_keep_alive_timer(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_keep_alive_timer.bits.kato = (g_data[2] << 24) + (g_data[3] << 16) +
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(g_data[4] << 8) + g_data[5];
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}
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static void feat_host_identifier(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_host_identifier.bits.exhid = g_data[2] & 0x01;
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}
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static void feat_rsv_notification_mask(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_rsv_notification_mask.bits.regpre = g_data[2] & 0x01;
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cmd->cmd.cdw11_bits.feat_rsv_notification_mask.bits.respre = (g_data[2] >> 1) & 0x01;
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cmd->cmd.cdw11_bits.feat_rsv_notification_mask.bits.resrel = (g_data[2] >> 2) & 0x01;
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}
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static void feat_rsv_persistence(struct fuzz_command *cmd)
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{
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cmd->cmd.cdw11_bits.feat_rsv_persistence.bits.ptpl = g_data[2] & 0x01;
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}
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static void
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fuzz_admin_set_features_command(struct fuzz_command *cmd)
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{
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memset(&cmd->cmd, 0, sizeof(cmd->cmd));
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cmd->cmd.opc = SPDK_NVME_OPC_SET_FEATURES;
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cmd->cmd.cdw10_bits.set_features.fid = g_data[0];
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cmd->cmd.cdw10_bits.set_features.sv = (g_data[1] >> 7) & 0x01;
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switch (cmd->cmd.cdw10_bits.set_features.fid) {
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case SPDK_NVME_FEAT_ARBITRATION:
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feat_arbitration(cmd);
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break;
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case SPDK_NVME_FEAT_POWER_MANAGEMENT:
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feat_power_management(cmd);
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break;
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case SPDK_NVME_FEAT_LBA_RANGE_TYPE:
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feat_lba_range_type(cmd);
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break;
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case SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD:
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feat_temperature_threshold(cmd);
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break;
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case SPDK_NVME_FEAT_ERROR_RECOVERY:
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feat_error_recover(cmd);
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break;
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case SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE:
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feat_volatile_write_cache(cmd);
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break;
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case SPDK_NVME_FEAT_NUMBER_OF_QUEUES:
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feat_number_of_queues(cmd);
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break;
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case SPDK_NVME_FEAT_INTERRUPT_COALESCING:
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feat_interrupt_coalescing(cmd);
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break;
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case SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION:
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feat_interrupt_vector_configuration(cmd);
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break;
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case SPDK_NVME_FEAT_WRITE_ATOMICITY:
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feat_write_atomicity(cmd);
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break;
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case SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION:
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feat_async_event_cfg(cmd);
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break;
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case SPDK_NVME_FEAT_KEEP_ALIVE_TIMER:
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feat_keep_alive_timer(cmd);
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break;
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case SPDK_NVME_FEAT_HOST_IDENTIFIER:
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feat_host_identifier(cmd);
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break;
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case SPDK_NVME_FEAT_HOST_RESERVE_MASK:
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feat_rsv_notification_mask(cmd);
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break;
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case SPDK_NVME_FEAT_HOST_RESERVE_PERSIST:
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feat_rsv_persistence(cmd);
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break;
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default:
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break;
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}
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/* Use g_data[2] through g_data[5] for feature-specific
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bits and set g_data[6] for cdw14 every iteration
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UUID index, bits 0-6 are used */
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cmd->cmd.cdw14 = (g_data[6] & 0x7f);
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g_data += 7;
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}
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static void
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fuzz_admin_get_features_command(struct fuzz_command *cmd)
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{
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memset(&cmd->cmd, 0, sizeof(cmd->cmd));
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cmd->cmd.opc = SPDK_NVME_OPC_GET_FEATURES;
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cmd->cmd.cdw10_bits.get_features.fid = g_data[0];
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cmd->cmd.cdw10_bits.get_features.sel = (g_data[1] >> 5) & 0x07;
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switch (cmd->cmd.cdw10_bits.set_features.fid) {
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case SPDK_NVME_FEAT_ARBITRATION:
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feat_arbitration(cmd);
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break;
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case SPDK_NVME_FEAT_POWER_MANAGEMENT:
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feat_power_management(cmd);
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break;
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case SPDK_NVME_FEAT_LBA_RANGE_TYPE:
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feat_lba_range_type(cmd);
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break;
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case SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD:
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feat_temperature_threshold(cmd);
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break;
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case SPDK_NVME_FEAT_ERROR_RECOVERY:
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feat_error_recover(cmd);
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break;
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case SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE:
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feat_volatile_write_cache(cmd);
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break;
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case SPDK_NVME_FEAT_NUMBER_OF_QUEUES:
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feat_number_of_queues(cmd);
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break;
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case SPDK_NVME_FEAT_INTERRUPT_COALESCING:
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feat_interrupt_coalescing(cmd);
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break;
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case SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION:
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feat_interrupt_vector_configuration(cmd);
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break;
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case SPDK_NVME_FEAT_WRITE_ATOMICITY:
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feat_write_atomicity(cmd);
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break;
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case SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION:
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feat_async_event_cfg(cmd);
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break;
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case SPDK_NVME_FEAT_KEEP_ALIVE_TIMER:
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feat_keep_alive_timer(cmd);
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break;
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default:
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break;
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}
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/* Use g_data[2] through g_data[5] for feature-specific
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bits and set g_data[6] for cdw14 every iteration
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UUID index, bits 0-6 are used */
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cmd->cmd.cdw14 = (g_data[6] & 0x7f);
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g_data += 7;
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}
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static void
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static void
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fuzz_nvm_read_command(struct fuzz_command *cmd)
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fuzz_nvm_read_command(struct fuzz_command *cmd)
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{
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{
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@ -494,6 +721,8 @@ static struct fuzz_type g_fuzzers[] = {
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{ .fn = fuzz_admin_security_send_command, .bytes_per_cmd = 8, .is_admin = true},
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{ .fn = fuzz_admin_security_send_command, .bytes_per_cmd = 8, .is_admin = true},
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{ .fn = fuzz_admin_directive_send_command, .bytes_per_cmd = 8, .is_admin = true},
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{ .fn = fuzz_admin_directive_send_command, .bytes_per_cmd = 8, .is_admin = true},
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{ .fn = fuzz_admin_directive_receive_command, .bytes_per_cmd = 8, .is_admin = true},
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{ .fn = fuzz_admin_directive_receive_command, .bytes_per_cmd = 8, .is_admin = true},
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{ .fn = fuzz_admin_set_features_command, .bytes_per_cmd = 7, .is_admin = true},
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{ .fn = fuzz_admin_get_features_command, .bytes_per_cmd = 7, .is_admin = true},
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{ .fn = fuzz_nvm_read_command, .bytes_per_cmd = 21, .is_admin = false},
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{ .fn = fuzz_nvm_read_command, .bytes_per_cmd = 21, .is_admin = false},
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{ .fn = fuzz_nvm_write_command, .bytes_per_cmd = 24, .is_admin = false},
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{ .fn = fuzz_nvm_write_command, .bytes_per_cmd = 24, .is_admin = false},
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{ .fn = fuzz_nvm_write_zeroes_command, .bytes_per_cmd = 20, .is_admin = false},
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{ .fn = fuzz_nvm_write_zeroes_command, .bytes_per_cmd = 20, .is_admin = false},
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