From 8332f9e47eb3b9097e04bc88f77c8cc98c4728ec Mon Sep 17 00:00:00 2001 From: Daniel Verkamp Date: Mon, 8 Feb 2016 16:06:31 -0700 Subject: [PATCH] nvme_intel: add spdk_ prefixes and tweak names Change-Id: I7c256bce365c92636f4f183e218117a1d7fe63d9 Signed-off-by: Daniel Verkamp --- examples/nvme/identify/identify.c | 102 ++++++++--------- examples/nvme/perf/perf.c | 28 ++--- include/spdk/nvme_intel.h | 108 +++++++++--------- lib/nvme/nvme_ctrlr.c | 34 +++--- .../nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c | 26 ++--- .../unit/nvme_ctrlr_cmd_c/nvme_ctrlr_cmd_ut.c | 46 ++++---- 6 files changed, 171 insertions(+), 173 deletions(-) diff --git a/examples/nvme/identify/identify.c b/examples/nvme/identify/identify.c index 8b7c58ee7..15b33e84b 100644 --- a/examples/nvme/identify/identify.c +++ b/examples/nvme/identify/identify.c @@ -57,9 +57,9 @@ static struct feature features[256]; static struct nvme_health_information_page *health_page; -static struct nvme_intel_smart_information_page *intel_smart_page; +static struct spdk_nvme_intel_smart_information_page *intel_smart_page; -static struct nvme_intel_temperature_page *intel_temperature_page; +static struct spdk_nvme_intel_temperature_page *intel_temperature_page; static bool g_hex_dump = false; @@ -201,7 +201,7 @@ get_intel_smart_log_page(struct nvme_controller *ctrlr) exit(1); } - if (nvme_ctrlr_cmd_get_log_page(ctrlr, NVME_INTEL_LOG_SMART, NVME_GLOBAL_NAMESPACE_TAG, + if (nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_SMART, NVME_GLOBAL_NAMESPACE_TAG, intel_smart_page, sizeof(*intel_smart_page), get_log_page_completion, NULL)) { printf("nvme_ctrlr_cmd_get_log_page() failed\n"); exit(1); @@ -222,7 +222,7 @@ get_intel_temperature_log_page(struct nvme_controller *ctrlr) exit(1); } - if (nvme_ctrlr_cmd_get_log_page(ctrlr, NVME_INTEL_LOG_TEMPERATURE, NVME_GLOBAL_NAMESPACE_TAG, + if (nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE, NVME_GLOBAL_NAMESPACE_TAG, intel_temperature_page, sizeof(*intel_temperature_page), get_log_page_completion, NULL)) { printf("nvme_ctrlr_cmd_get_log_page() failed\n"); exit(1); @@ -244,14 +244,14 @@ get_log_pages(struct nvme_controller *ctrlr) ctrlr_data = nvme_ctrlr_get_data(ctrlr); if (ctrlr_data->vid == SPDK_PCI_VID_INTEL) { - if (nvme_ctrlr_is_log_page_supported(ctrlr, NVME_INTEL_LOG_SMART)) { + if (nvme_ctrlr_is_log_page_supported(ctrlr, SPDK_NVME_INTEL_LOG_SMART)) { if (get_intel_smart_log_page(ctrlr) == 0) { outstanding_commands++; } else { printf("Get Log Page (Intel SMART/health) failed\n"); } } - if (nvme_ctrlr_is_log_page_supported(ctrlr, NVME_INTEL_LOG_TEMPERATURE)) { + if (nvme_ctrlr_is_log_page_supported(ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE)) { if (get_intel_temperature_log_page(ctrlr) == 0) { outstanding_commands++; } else { @@ -590,123 +590,119 @@ print_controller(struct nvme_controller *ctrlr, struct spdk_pci_device *pci_dev) printf("Intel Health Information\n"); printf("==================\n"); for (i = 0; - i < sizeof(intel_smart_page->nvme_intel_smart_attributes) / sizeof( - intel_smart_page->nvme_intel_smart_attributes[0]); i++) { - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_PROGRAM_FAIL_COUNT) { + i < sizeof(intel_smart_page->attributes) / sizeof(intel_smart_page->attributes[0]); i++) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_PROGRAM_FAIL_COUNT) { printf("Program Fail Count:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_ERASE_FAIL_COUNT) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_ERASE_FAIL_COUNT) { printf("Erase Fail Count:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_WEAR_LEVELING_COUNT) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_WEAR_LEVELING_COUNT) { printf("Wear Leveling Count:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: \n"); printf(" Min: "); - print_uint_var_dec(&intel_smart_page->nvme_intel_smart_attributes[i].raw_value[0], 2); + print_uint_var_dec(&intel_smart_page->attributes[i].raw_value[0], 2); printf("\n"); printf(" Max: "); - print_uint_var_dec(&intel_smart_page->nvme_intel_smart_attributes[i].raw_value[2], 2); + print_uint_var_dec(&intel_smart_page->attributes[i].raw_value[2], 2); printf("\n"); printf(" Avg: "); - print_uint_var_dec(&intel_smart_page->nvme_intel_smart_attributes[i].raw_value[4], 2); + print_uint_var_dec(&intel_smart_page->attributes[i].raw_value[4], 2); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_E2E_ERROR_COUNT) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_E2E_ERROR_COUNT) { printf("End to End Error Detection Count:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_CRC_ERROR_COUNT) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_CRC_ERROR_COUNT) { printf("CRC Error Count:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_MEDIA_WEAR) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_MEDIA_WEAR) { printf("Timed Workload, Media Wear:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == - NVME_INTEL_SMART_HOST_READ_PERCENTAGE) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_HOST_READ_PERCENTAGE) { printf("Timed Workload, Host Read/Write Ratio:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("%%"); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_TIMER) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_TIMER) { printf("Timed Workload, Timer:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == - NVME_INTEL_SMART_THERMAL_THROTTLE_STATUS) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_THERMAL_THROTTLE_STATUS) { printf("Thermal Throttle Status:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: \n"); - printf(" Percentage: %d%%\n", intel_smart_page->nvme_intel_smart_attributes[i].raw_value[0]); + printf(" Percentage: %d%%\n", intel_smart_page->attributes[i].raw_value[0]); printf(" Throttling Event Count: "); - print_uint_var_dec(&intel_smart_page->nvme_intel_smart_attributes[i].raw_value[1], 4); + print_uint_var_dec(&intel_smart_page->attributes[i].raw_value[1], 4); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == - NVME_INTEL_SMART_RETRY_BUFFER_OVERFLOW_COUNTER) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_RETRY_BUFFER_OVERFLOW_COUNTER) { printf("Retry Buffer Overflow Counter:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_PLL_LOCK_LOSS_COUNT) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_PLL_LOCK_LOSS_COUNT) { printf("PLL Lock Loss Count:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_NAND_BYTES_WRITTEN) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_NAND_BYTES_WRITTEN) { printf("NAND Bytes Written:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } - if (intel_smart_page->nvme_intel_smart_attributes[i].code == NVME_INTEL_SMART_HOST_BYTES_WRITTEN) { + if (intel_smart_page->attributes[i].code == SPDK_NVME_INTEL_SMART_HOST_BYTES_WRITTEN) { printf("Host Bytes Written:\n"); printf(" Normalized Value : %d\n", - intel_smart_page->nvme_intel_smart_attributes[i].normalized_value); + intel_smart_page->attributes[i].normalized_value); printf(" Current Raw Value: "); - print_uint_var_dec(intel_smart_page->nvme_intel_smart_attributes[i].raw_value, 6); + print_uint_var_dec(intel_smart_page->attributes[i].raw_value, 6); printf("\n"); } } diff --git a/examples/nvme/perf/perf.c b/examples/nvme/perf/perf.c index b629b3b61..38e056921 100644 --- a/examples/nvme/perf/perf.c +++ b/examples/nvme/perf/perf.c @@ -56,7 +56,7 @@ struct ctrlr_entry { struct nvme_controller *ctrlr; - struct nvme_intel_rw_latency_page *latency_page; + struct spdk_nvme_intel_rw_latency_page *latency_page; struct ctrlr_entry *next; char name[1024]; }; @@ -194,16 +194,16 @@ static void set_latency_tracking_feature(struct nvme_controller *ctrlr, bool enable) { int res; - union nvme_intel_enable_latency_tracking_feature enable_latency_tracking; + union spdk_nvme_intel_feat_latency_tracking latency_tracking; if (enable) { - enable_latency_tracking.bits.enable = 0x01; + latency_tracking.bits.enable = 0x01; } else { - enable_latency_tracking.bits.enable = 0x00; + latency_tracking.bits.enable = 0x00; } - res = nvme_ctrlr_cmd_set_feature(ctrlr, NVME_INTEL_FEAT_LATENCY_TRACKING, - enable_latency_tracking.raw, 0, NULL, 0, enable_latency_tracking_complete, NULL); + res = nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING, + latency_tracking.raw, 0, NULL, 0, enable_latency_tracking_complete, NULL); if (res) { printf("fail to allocate nvme request.\n"); return; @@ -227,7 +227,8 @@ register_ctrlr(struct nvme_controller *ctrlr) exit(1); } - entry->latency_page = rte_zmalloc("nvme latency", sizeof(struct nvme_intel_rw_latency_page), 4096); + entry->latency_page = rte_zmalloc("nvme latency", sizeof(struct spdk_nvme_intel_rw_latency_page), + 4096); if (entry->latency_page == NULL) { printf("Allocation error (latency page)\n"); exit(1); @@ -240,7 +241,7 @@ register_ctrlr(struct nvme_controller *ctrlr) g_controllers = entry; if (g_latency_tracking_enable && - nvme_ctrlr_is_feature_supported(ctrlr, NVME_INTEL_FEAT_LATENCY_TRACKING)) + nvme_ctrlr_is_feature_supported(ctrlr, SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING)) set_latency_tracking_feature(ctrlr, true); num_ns = nvme_ctrlr_get_num_ns(ctrlr); @@ -605,7 +606,7 @@ print_latency_page(struct ctrlr_entry *entry) } static void -print_latency_statistics(const char *op_name, enum nvme_intel_log_page log_page) +print_latency_statistics(const char *op_name, enum spdk_nvme_intel_log_page log_page) { struct ctrlr_entry *ctrlr; @@ -615,7 +616,8 @@ print_latency_statistics(const char *op_name, enum nvme_intel_log_page log_page) while (ctrlr) { if (nvme_ctrlr_is_log_page_supported(ctrlr->ctrlr, log_page)) { if (nvme_ctrlr_cmd_get_log_page(ctrlr->ctrlr, log_page, NVME_GLOBAL_NAMESPACE_TAG, - ctrlr->latency_page, sizeof(struct nvme_intel_rw_latency_page), enable_latency_tracking_complete, + ctrlr->latency_page, sizeof(struct spdk_nvme_intel_rw_latency_page), + enable_latency_tracking_complete, NULL)) { printf("nvme_ctrlr_cmd_get_log_page() failed\n"); exit(1); @@ -652,10 +654,10 @@ print_stats(void) print_performance(); if (g_latency_tracking_enable) { if (g_rw_percentage != 0) { - print_latency_statistics("Read", NVME_INTEL_LOG_READ_CMD_LATENCY); + print_latency_statistics("Read", SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); } if (g_rw_percentage != 100) { - print_latency_statistics("Write", NVME_INTEL_LOG_WRITE_CMD_LATENCY); + print_latency_statistics("Write", SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY); } } } @@ -874,7 +876,7 @@ unregister_controllers(void) struct ctrlr_entry *next = entry->next; rte_free(entry->latency_page); if (g_latency_tracking_enable && - nvme_ctrlr_is_feature_supported(entry->ctrlr, NVME_INTEL_FEAT_LATENCY_TRACKING)) + nvme_ctrlr_is_feature_supported(entry->ctrlr, SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING)) set_latency_tracking_feature(entry->ctrlr, false); nvme_detach(entry->ctrlr); free(entry); diff --git a/include/spdk/nvme_intel.h b/include/spdk/nvme_intel.h index 421c45868..be1055d3c 100644 --- a/include/spdk/nvme_intel.h +++ b/include/spdk/nvme_intel.h @@ -43,51 +43,50 @@ * \file * * reference: - * http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ - * ssd-dc-p3700-spec.pdf + * http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ssd-dc-p3700-spec.pdf */ -enum nvme_intel_feature { - NVME_INTEL_FEAT_MAX_LBA = 0xC1, - NVME_INTEL_FEAT_NATIVE_MAX_LBA = 0xC2, - NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING = 0xC6, - NVME_INTEL_FEAT_SMBUS_ADDRESS = 0xC8, - NVME_INTEL_FEAT_LED_PATTERN = 0xC9, - NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS = 0xD5, - NVME_INTEL_FEAT_LATENCY_TRACKING = 0xE2, +enum spdk_nvme_intel_feat { + SPDK_NVME_INTEL_FEAT_MAX_LBA = 0xC1, + SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA = 0xC2, + SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING = 0xC6, + SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS = 0xC8, + SPDK_NVME_INTEL_FEAT_LED_PATTERN = 0xC9, + SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS = 0xD5, + SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING = 0xE2, }; -enum nvme_intel_set_max_lba_command_status_code { - NVME_INTEL_EXCEEDS_AVAILABLE_CAPACITY = 0xC0, - NVME_INTEL_SMALLER_THAN_MIN_LIMIT = 0xC1, - NVME_INTEL_SMALLER_THAN_NS_REQUIREMENTS = 0xC2, +enum spdk_nvme_intel_set_max_lba_command_status_code { + SPDK_NVME_INTEL_EXCEEDS_AVAILABLE_CAPACITY = 0xC0, + SPDK_NVME_INTEL_SMALLER_THAN_MIN_LIMIT = 0xC1, + SPDK_NVME_INTEL_SMALLER_THAN_NS_REQUIREMENTS = 0xC2, }; -enum nvme_intel_log_page { - NVME_INTEL_LOG_PAGE_DIRECTORY = 0xC0, - NVME_INTEL_LOG_READ_CMD_LATENCY = 0xC1, - NVME_INTEL_LOG_WRITE_CMD_LATENCY = 0xC2, - NVME_INTEL_LOG_TEMPERATURE = 0xC5, - NVME_INTEL_LOG_SMART = 0xCA, +enum spdk_nvme_intel_log_page { + SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY = 0xC0, + SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY = 0xC1, + SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY = 0xC2, + SPDK_NVME_INTEL_LOG_TEMPERATURE = 0xC5, + SPDK_NVME_INTEL_LOG_SMART = 0xCA, }; -enum nvme_intel_smart_attribute_code { - NVME_INTEL_SMART_PROGRAM_FAIL_COUNT = 0xAB, - NVME_INTEL_SMART_ERASE_FAIL_COUNT = 0xAC, - NVME_INTEL_SMART_WEAR_LEVELING_COUNT = 0xAD, - NVME_INTEL_SMART_E2E_ERROR_COUNT = 0xB8, - NVME_INTEL_SMART_CRC_ERROR_COUNT = 0xC7, - NVME_INTEL_SMART_MEDIA_WEAR = 0xE2, - NVME_INTEL_SMART_HOST_READ_PERCENTAGE = 0xE3, - NVME_INTEL_SMART_TIMER = 0xE4, - NVME_INTEL_SMART_THERMAL_THROTTLE_STATUS = 0xEA, - NVME_INTEL_SMART_RETRY_BUFFER_OVERFLOW_COUNTER = 0xF0, - NVME_INTEL_SMART_PLL_LOCK_LOSS_COUNT = 0xF3, - NVME_INTEL_SMART_NAND_BYTES_WRITTEN = 0xF4, - NVME_INTEL_SMART_HOST_BYTES_WRITTEN = 0xF5, +enum spdk_nvme_intel_smart_attribute_code { + SPDK_NVME_INTEL_SMART_PROGRAM_FAIL_COUNT = 0xAB, + SPDK_NVME_INTEL_SMART_ERASE_FAIL_COUNT = 0xAC, + SPDK_NVME_INTEL_SMART_WEAR_LEVELING_COUNT = 0xAD, + SPDK_NVME_INTEL_SMART_E2E_ERROR_COUNT = 0xB8, + SPDK_NVME_INTEL_SMART_CRC_ERROR_COUNT = 0xC7, + SPDK_NVME_INTEL_SMART_MEDIA_WEAR = 0xE2, + SPDK_NVME_INTEL_SMART_HOST_READ_PERCENTAGE = 0xE3, + SPDK_NVME_INTEL_SMART_TIMER = 0xE4, + SPDK_NVME_INTEL_SMART_THERMAL_THROTTLE_STATUS = 0xEA, + SPDK_NVME_INTEL_SMART_RETRY_BUFFER_OVERFLOW_COUNTER = 0xF0, + SPDK_NVME_INTEL_SMART_PLL_LOCK_LOSS_COUNT = 0xF3, + SPDK_NVME_INTEL_SMART_NAND_BYTES_WRITTEN = 0xF4, + SPDK_NVME_INTEL_SMART_HOST_BYTES_WRITTEN = 0xF5, }; -struct nvme_intel_log_page_directory { +struct spdk_nvme_intel_log_page_directory { uint8_t version[2]; uint8_t reserved[384]; uint8_t read_latency_log_len; @@ -99,18 +98,18 @@ struct nvme_intel_log_page_directory { uint8_t smart_log_len; uint8_t reserved5[107]; }; -SPDK_STATIC_ASSERT(sizeof(struct nvme_intel_log_page_directory) == 512, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_log_page_directory) == 512, "Incorrect size"); -struct nvme_intel_rw_latency_page { +struct spdk_nvme_intel_rw_latency_page { uint16_t major_revison; uint16_t minor_revison; uint32_t buckets_32us[32]; uint32_t buckets_1ms[31]; uint32_t buckets_32ms[31]; }; -SPDK_STATIC_ASSERT(sizeof(struct nvme_intel_rw_latency_page) == 380, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_rw_latency_page) == 380, "Incorrect size"); -struct nvme_intel_temperature_page { +struct spdk_nvme_intel_temperature_page { uint64_t current_temperature; uint64_t shutdown_flag_last; uint64_t shutdown_flag_life; @@ -122,9 +121,9 @@ struct nvme_intel_temperature_page { uint64_t specified_min_op_temperature; uint64_t estimated_offset; }; -SPDK_STATIC_ASSERT(sizeof(struct nvme_intel_temperature_page) == 112, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_temperature_page) == 112, "Incorrect size"); -struct nvme_intel_smart_attribute { +struct spdk_nvme_intel_smart_attribute { uint8_t code; uint8_t reserved[2]; uint8_t normalized_value; @@ -133,12 +132,12 @@ struct nvme_intel_smart_attribute { uint8_t reserved3; }; -struct __attribute__((packed)) nvme_intel_smart_information_page { - struct nvme_intel_smart_attribute nvme_intel_smart_attributes[13]; +struct __attribute__((packed)) spdk_nvme_intel_smart_information_page { + struct spdk_nvme_intel_smart_attribute attributes[13]; }; -SPDK_STATIC_ASSERT(sizeof(struct nvme_intel_smart_information_page) == 156, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_smart_information_page) == 156, "Incorrect size"); -union nvme_intel_power_governor_feature { +union spdk_nvme_intel_feat_power_governor { uint32_t raw; struct { /** power governor setting : 00h = 25W 01h = 20W 02h = 10W */ @@ -146,9 +145,9 @@ union nvme_intel_power_governor_feature { uint32_t reserved : 24; } bits; }; -SPDK_STATIC_ASSERT(sizeof(union nvme_intel_power_governor_feature) == 4, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_power_governor) == 4, "Incorrect size"); -union nvme_intel_smbus_address_feature { +union spdk_nvme_intel_feat_smbus_address { uint32_t raw; struct { uint32_t reserved : 1; @@ -156,18 +155,18 @@ union nvme_intel_smbus_address_feature { uint32_t reserved2 : 23; } bits; }; -SPDK_STATIC_ASSERT(sizeof(union nvme_intel_smbus_address_feature) == 4, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_smbus_address) == 4, "Incorrect size"); -union nvme_intel_led_pattern_feature { +union spdk_nvme_intel_feat_led_pattern { uint32_t raw; struct { uint32_t feature_options : 24; uint32_t value : 8; } bits; }; -SPDK_STATIC_ASSERT(sizeof(union nvme_intel_led_pattern_feature) == 4, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_led_pattern) == 4, "Incorrect size"); -union nvme_intel_reset_timed_workload_counters_feature { +union spdk_nvme_intel_feat_reset_timed_workload_counters { uint32_t raw; struct { /** @@ -178,10 +177,10 @@ union nvme_intel_reset_timed_workload_counters_feature { uint32_t reserved : 31; } bits; }; -SPDK_STATIC_ASSERT(sizeof(union nvme_intel_reset_timed_workload_counters_feature) == 4, +SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_reset_timed_workload_counters) == 4, "Incorrect size"); -union nvme_intel_enable_latency_tracking_feature { +union spdk_nvme_intel_feat_latency_tracking { uint32_t raw; struct { /** @@ -192,5 +191,6 @@ union nvme_intel_enable_latency_tracking_feature { uint32_t enable : 32; } bits; }; -SPDK_STATIC_ASSERT(sizeof(union nvme_intel_enable_latency_tracking_feature) == 4, "Incorrect size"); +SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_latency_tracking) == 4, "Incorrect size"); + #endif diff --git a/lib/nvme/nvme_ctrlr.c b/lib/nvme/nvme_ctrlr.c index 0da0b0129..d56f34ab1 100644 --- a/lib/nvme/nvme_ctrlr.c +++ b/lib/nvme/nvme_ctrlr.c @@ -44,7 +44,7 @@ static int nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, static void nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr, - struct nvme_intel_log_page_directory *log_page_directory) + struct spdk_nvme_intel_log_page_directory *log_page_directory) { struct spdk_pci_device *dev; struct pci_id pci_id; @@ -58,21 +58,21 @@ nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr, pci_id.sub_vendor_id = spdk_pci_device_get_subvendor_id(dev); pci_id.sub_dev_id = spdk_pci_device_get_subdevice_id(dev); - ctrlr->log_page_supported[NVME_INTEL_LOG_PAGE_DIRECTORY] = true; + ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true; if (log_page_directory->read_latency_log_len || nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_READ_LATENCY)) { - ctrlr->log_page_supported[NVME_INTEL_LOG_READ_CMD_LATENCY] = true; + ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true; } if (log_page_directory->write_latency_log_len || nvme_intel_has_quirk(&pci_id, NVME_INTEL_QUIRK_WRITE_LATENCY)) { - ctrlr->log_page_supported[NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true; + ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true; } if (log_page_directory->temperature_statistics_log_len) { - ctrlr->log_page_supported[NVME_INTEL_LOG_TEMPERATURE] = true; + ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true; } if (log_page_directory->smart_log_len) { - ctrlr->log_page_supported[NVME_INTEL_LOG_SMART] = true; + ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true; } } @@ -80,10 +80,10 @@ static int nvme_ctrlr_set_intel_support_log_pages(struct nvme_controller *ctrlr) { uint64_t phys_addr = 0; struct nvme_completion_poll_status status; - struct nvme_intel_log_page_directory *log_page_directory; + struct spdk_nvme_intel_log_page_directory *log_page_directory; log_page_directory = nvme_malloc("nvme_log_page_directory", - sizeof(struct nvme_intel_log_page_directory), + sizeof(struct spdk_nvme_intel_log_page_directory), 64, &phys_addr); if (log_page_directory == NULL) { nvme_printf(NULL, "could not allocate log_page_directory\n"); @@ -91,8 +91,8 @@ static int nvme_ctrlr_set_intel_support_log_pages(struct nvme_controller *ctrlr) } status.done = false; - nvme_ctrlr_cmd_get_log_page(ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY, NVME_GLOBAL_NAMESPACE_TAG, - log_page_directory, sizeof(struct nvme_intel_log_page_directory), + nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY, NVME_GLOBAL_NAMESPACE_TAG, + log_page_directory, sizeof(struct spdk_nvme_intel_log_page_directory), nvme_completion_poll_cb, &status); while (status.done == false) { @@ -128,13 +128,13 @@ nvme_ctrlr_set_supported_log_pages(struct nvme_controller *ctrlr) static void nvme_ctrlr_set_intel_supported_features(struct nvme_controller *ctrlr) { - ctrlr->feature_supported[NVME_INTEL_FEAT_MAX_LBA] = true; - ctrlr->feature_supported[NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true; - ctrlr->feature_supported[NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true; - ctrlr->feature_supported[NVME_INTEL_FEAT_SMBUS_ADDRESS] = true; - ctrlr->feature_supported[NVME_INTEL_FEAT_LED_PATTERN] = true; - ctrlr->feature_supported[NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true; - ctrlr->feature_supported[NVME_INTEL_FEAT_LATENCY_TRACKING] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true; + ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true; } static void diff --git a/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c b/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c index eb9e8d7a1..3c6ae1063 100644 --- a/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c +++ b/test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c @@ -228,14 +228,14 @@ static void test_nvme_ctrlr_construct_intel_support_log_page_list(void) { bool res; - struct nvme_controller ctrlr = {}; - struct nvme_intel_log_page_directory payload = {}; + struct nvme_controller ctrlr = {}; + struct spdk_nvme_intel_log_page_directory payload = {}; /* set a invalid vendor id */ ctrlr.cdata.vid = 0xFFFF; nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); CU_ASSERT(res == false); /* set valid vendor id and log page directory*/ @@ -244,13 +244,13 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void) memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY); CU_ASSERT(res == true); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); CU_ASSERT(res == true); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_READ_CMD_LATENCY); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); CU_ASSERT(res == false); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_SMART); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART); CU_ASSERT(res == false); /* set valid vendor id, device id and sub device id*/ @@ -263,13 +263,13 @@ test_nvme_ctrlr_construct_intel_support_log_page_list(void) memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY); CU_ASSERT(res == true); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_TEMPERATURE); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); CU_ASSERT(res == false); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_READ_CMD_LATENCY); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); CU_ASSERT(res == true); - res = nvme_ctrlr_is_log_page_supported(&ctrlr, NVME_INTEL_LOG_SMART); + res = nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART); CU_ASSERT(res == false); } @@ -284,14 +284,14 @@ test_nvme_ctrlr_set_supported_features(void) nvme_ctrlr_set_supported_features(&ctrlr); res = nvme_ctrlr_is_feature_supported(&ctrlr, NVME_FEAT_ARBITRATION); CU_ASSERT(res == true); - res = nvme_ctrlr_is_feature_supported(&ctrlr, NVME_INTEL_FEAT_MAX_LBA); + res = nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA); CU_ASSERT(res == false); ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; nvme_ctrlr_set_supported_features(&ctrlr); res = nvme_ctrlr_is_feature_supported(&ctrlr, NVME_FEAT_ARBITRATION); CU_ASSERT(res == true); - res = nvme_ctrlr_is_feature_supported(&ctrlr, NVME_INTEL_FEAT_MAX_LBA); + res = nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA); CU_ASSERT(res == true); } diff --git a/test/lib/nvme/unit/nvme_ctrlr_cmd_c/nvme_ctrlr_cmd_ut.c b/test/lib/nvme/unit/nvme_ctrlr_cmd_c/nvme_ctrlr_cmd_ut.c index 46262a325..a8e5b5aad 100644 --- a/test/lib/nvme/unit/nvme_ctrlr_cmd_c/nvme_ctrlr_cmd_ut.c +++ b/test/lib/nvme/unit/nvme_ctrlr_cmd_c/nvme_ctrlr_cmd_ut.c @@ -127,8 +127,9 @@ static void verify_intel_smart_log_page(struct nvme_request *req) CU_ASSERT(req->cmd.opc == NVME_OPC_GET_LOG_PAGE); CU_ASSERT(req->cmd.nsid == health_log_nsid); - temp_cdw10 = ((sizeof(struct nvme_intel_smart_information_page) / sizeof(uint32_t) - 1) << 16) | - NVME_INTEL_LOG_SMART; + temp_cdw10 = ((sizeof(struct spdk_nvme_intel_smart_information_page) / + sizeof(uint32_t) - 1) << 16) | + SPDK_NVME_INTEL_LOG_SMART; CU_ASSERT(req->cmd.cdw10 == temp_cdw10); } @@ -138,8 +139,8 @@ static void verify_intel_temperature_log_page(struct nvme_request *req) CU_ASSERT(req->cmd.opc == NVME_OPC_GET_LOG_PAGE); - temp_cdw10 = ((sizeof(struct nvme_intel_temperature_page) / sizeof(uint32_t) - 1) << 16) | - NVME_INTEL_LOG_TEMPERATURE; + temp_cdw10 = ((sizeof(struct spdk_nvme_intel_temperature_page) / sizeof(uint32_t) - 1) << 16) | + SPDK_NVME_INTEL_LOG_TEMPERATURE; CU_ASSERT(req->cmd.cdw10 == temp_cdw10); } @@ -149,8 +150,8 @@ static void verify_intel_read_latency_log_page(struct nvme_request *req) CU_ASSERT(req->cmd.opc == NVME_OPC_GET_LOG_PAGE); - temp_cdw10 = ((sizeof(struct nvme_intel_rw_latency_page) / sizeof(uint32_t) - 1) << 16) | - NVME_INTEL_LOG_READ_CMD_LATENCY; + temp_cdw10 = ((sizeof(struct spdk_nvme_intel_rw_latency_page) / sizeof(uint32_t) - 1) << 16) | + SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY; CU_ASSERT(req->cmd.cdw10 == temp_cdw10); } @@ -160,8 +161,8 @@ static void verify_intel_write_latency_log_page(struct nvme_request *req) CU_ASSERT(req->cmd.opc == NVME_OPC_GET_LOG_PAGE); - temp_cdw10 = ((sizeof(struct nvme_intel_rw_latency_page) / sizeof(uint32_t) - 1) << 16) | - NVME_INTEL_LOG_WRITE_CMD_LATENCY; + temp_cdw10 = ((sizeof(struct spdk_nvme_intel_rw_latency_page) / sizeof(uint32_t) - 1) << 16) | + SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY; CU_ASSERT(req->cmd.cdw10 == temp_cdw10); } @@ -171,8 +172,8 @@ static void verify_intel_get_log_page_directory(struct nvme_request *req) CU_ASSERT(req->cmd.opc == NVME_OPC_GET_LOG_PAGE); - temp_cdw10 = ((sizeof(struct nvme_intel_log_page_directory) / sizeof(uint32_t) - 1) << 16) | - NVME_INTEL_LOG_PAGE_DIRECTORY; + temp_cdw10 = ((sizeof(struct spdk_nvme_intel_log_page_directory) / sizeof(uint32_t) - 1) << 16) | + SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY; CU_ASSERT(req->cmd.cdw10 == temp_cdw10); } @@ -272,34 +273,33 @@ test_error_get_log_page(void) static void test_intel_smart_get_log_page(void) { struct nvme_controller ctrlr = {}; - struct nvme_intel_smart_information_page payload = {}; + struct spdk_nvme_intel_smart_information_page payload = {}; verify_fn = verify_intel_smart_log_page; - nvme_ctrlr_cmd_get_log_page(&ctrlr, NVME_INTEL_LOG_SMART, health_log_nsid, &payload, + nvme_ctrlr_cmd_get_log_page(&ctrlr, SPDK_NVME_INTEL_LOG_SMART, health_log_nsid, &payload, sizeof(payload), NULL, NULL); } static void test_intel_temperature_get_log_page(void) { struct nvme_controller ctrlr = {}; - struct nvme_intel_temperature_page payload = {}; + struct spdk_nvme_intel_temperature_page payload = {}; verify_fn = verify_intel_temperature_log_page; - nvme_ctrlr_cmd_get_log_page(&ctrlr, NVME_INTEL_LOG_TEMPERATURE, NVME_GLOBAL_NAMESPACE_TAG, - &payload, - sizeof(payload), NULL, NULL); + nvme_ctrlr_cmd_get_log_page(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE, NVME_GLOBAL_NAMESPACE_TAG, + &payload, sizeof(payload), NULL, NULL); } static void test_intel_read_latency_get_log_page(void) { struct nvme_controller ctrlr = {}; - struct nvme_intel_rw_latency_page payload = {}; + struct spdk_nvme_intel_rw_latency_page payload = {}; verify_fn = verify_intel_read_latency_log_page; - nvme_ctrlr_cmd_get_log_page(&ctrlr, NVME_INTEL_LOG_READ_CMD_LATENCY, + nvme_ctrlr_cmd_get_log_page(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY, NVME_GLOBAL_NAMESPACE_TAG, &payload, sizeof(payload), NULL, NULL); } @@ -307,23 +307,23 @@ static void test_intel_read_latency_get_log_page(void) static void test_intel_write_latency_get_log_page(void) { struct nvme_controller ctrlr = {}; - struct nvme_intel_rw_latency_page payload = {}; + struct spdk_nvme_intel_rw_latency_page payload = {}; verify_fn = verify_intel_write_latency_log_page; - nvme_ctrlr_cmd_get_log_page(&ctrlr, NVME_INTEL_LOG_WRITE_CMD_LATENCY, + nvme_ctrlr_cmd_get_log_page(&ctrlr, SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY, NVME_GLOBAL_NAMESPACE_TAG, &payload, sizeof(payload), NULL, NULL); } static void test_intel_get_log_page_directory(void) { - struct nvme_controller ctrlr = {}; - struct nvme_intel_log_page_directory payload = {}; + struct nvme_controller ctrlr = {}; + struct spdk_nvme_intel_log_page_directory payload = {}; verify_fn = verify_intel_get_log_page_directory; - nvme_ctrlr_cmd_get_log_page(&ctrlr, NVME_INTEL_LOG_PAGE_DIRECTORY, NVME_GLOBAL_NAMESPACE_TAG, + nvme_ctrlr_cmd_get_log_page(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY, NVME_GLOBAL_NAMESPACE_TAG, &payload, sizeof(payload), NULL, NULL); }