From 73050d511a1a27ee684fd008982880ab53005951 Mon Sep 17 00:00:00 2001 From: Konrad Sztyber Date: Tue, 29 Jun 2021 16:27:37 +0200 Subject: [PATCH] nvme: enable the controller asynchronously Signed-off-by: Jim Harris Signed-off-by: Konrad Sztyber Change-Id: I2a8116bbb95f6835cd37118f81ec1144501c5b3a Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/8620 Community-CI: Broadcom CI Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins Reviewed-by: Shuhei Matsumoto Reviewed-by: Aleksey Marchuk Reviewed-by: Ben Walker --- lib/nvme/nvme_ctrlr.c | 29 ++++++++++++++----- lib/nvme/nvme_internal.h | 5 ++++ .../lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c | 7 ----- 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/lib/nvme/nvme_ctrlr.c b/lib/nvme/nvme_ctrlr.c index 7bf76a881..59d769d21 100644 --- a/lib/nvme/nvme_ctrlr.c +++ b/lib/nvme/nvme_ctrlr.c @@ -1125,6 +1125,21 @@ nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr) return ctrlr->cap.bits.to * 500; } +static void +nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) +{ + struct spdk_nvme_ctrlr *ctrlr = ctx; + + if (spdk_nvme_cpl_is_error(cpl)) { + NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n"); + nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); + return; + } + + nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, + nvme_ctrlr_get_ready_timeout(ctrlr)); +} + static int nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) { @@ -1137,11 +1152,7 @@ nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) return rc; } - if (nvme_ctrlr_get_cc(ctrlr, &cc)) { - NVME_CTRLR_ERRLOG(ctrlr, "get_cc() failed\n"); - return -EIO; - } - + cc.raw = ctrlr->process_init_cc.raw; if (cc.bits.en != 0) { NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n"); return -EINVAL; @@ -1211,8 +1222,9 @@ nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) } cc.bits.ams = ctrlr->opts.arb_mechanism; + ctrlr->process_init_cc.raw = cc.raw; - if (nvme_ctrlr_set_cc(ctrlr, &cc)) { + if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) { NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n"); return -EIO; } @@ -1280,6 +1292,8 @@ nvme_ctrlr_state_string(enum nvme_ctrlr_state state) return "disable and wait for CSTS.RDY = 0 reg"; case NVME_CTRLR_STATE_ENABLE: return "enable controller by writing CC.EN = 1"; + case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC: + return "enable controller by writing CC.EN = 1 reg"; case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: return "wait for CSTS.RDY = 1"; case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE: @@ -3709,8 +3723,8 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) case NVME_CTRLR_STATE_ENABLE: NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n"); + nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms); rc = nvme_ctrlr_enable(ctrlr); - nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms); return rc; case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: @@ -3810,6 +3824,7 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC: case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS: + case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC: case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY: case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC: case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG: diff --git a/lib/nvme/nvme_internal.h b/lib/nvme/nvme_internal.h index b157a29b0..172652bc0 100644 --- a/lib/nvme/nvme_internal.h +++ b/lib/nvme/nvme_internal.h @@ -623,6 +623,11 @@ enum nvme_ctrlr_state { */ NVME_CTRLR_STATE_ENABLE, + /** + * Waiting for CC register to be written as part of enabling the controller. + */ + NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, + /** * Waiting for CSTS.RDY to transition from 0 to 1 after enabling the controller. */ diff --git a/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c b/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c index 40a475e82..085f19876 100644 --- a/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c +++ b/test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c @@ -889,7 +889,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /* @@ -921,7 +920,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /* @@ -953,7 +951,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /* @@ -1113,7 +1110,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /* @@ -1145,7 +1141,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /* @@ -1270,7 +1265,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /* @@ -1336,7 +1330,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); - CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); /*