From 438243485553180c317d0c296ee0045e646fd742 Mon Sep 17 00:00:00 2001
From: PepperJo <jpf@zurich.ibm.com>
Date: Thu, 12 Oct 2017 15:07:23 +0200
Subject: [PATCH] nvme/pcie: add memory barrier process completions

Because ppc64 has less strict memory ordering behaviour
than x86 we need to introduce a memory barrier when
polling for completions due to possible reordering
of tracker and cpl access.

Change-Id: Id17116c38b2ba69154c175c539fc97c60897deb0
Signed-off-by: Jonas Pfefferle <jpf@zurich.ibm.com>
Reviewed-on: https://review.gerrithub.io/383728
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
---
 lib/nvme/nvme_pcie.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/lib/nvme/nvme_pcie.c b/lib/nvme/nvme_pcie.c
index 03ff9a111..6db0db963 100644
--- a/lib/nvme/nvme_pcie.c
+++ b/lib/nvme/nvme_pcie.c
@@ -1907,6 +1907,14 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_
 
 		if (cpl->status.p != pqpair->phase)
 			break;
+#ifdef __PPC64__
+		/*
+		 * This memory barrier prevents reordering of:
+		 * - load after store from/to tr
+		 * - load after load cpl phase and cpl cid
+		 */
+		spdk_mb();
+#endif
 
 		tr = &pqpair->tr[cpl->cid];