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idxd: Introduce grptbl and wqtbl structs to further simplify

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initialization

We can make the structs do all of the offset math for us.

Change-Id: Ibe6d86c2abc58655c1354f1eb31091c95cfb283c
Signed-off-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/11487
Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
Community-CI: Mellanox Build Bot
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com>
Reviewed-by: Paul Luse <paul.e.luse@intel.com>
This commit is contained in:
Ben Walker 2022-02-03 14:18:31 -07:00 committed by Tomasz Zawadzki
parent 7a9b023008
commit 3b9c7ade6c
2 changed files with 29 additions and 17 deletions
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15
include/spdk/idxd_spec.h
View File

@ -542,8 +542,17 @@ struct idxd_grpcfg {
uint64_t wqs[4];
uint64_t engines;
union idxd_group_flags flags;
/* This is not part of the definition, but in practice the stride in the table
* is 64 bytes. */
uint32_t reserved0;
uint64_t reserved1[2];
};
SPDK_STATIC_ASSERT(sizeof(struct idxd_grpcfg) == 64, "size mismatch");
struct idxd_grptbl {
struct idxd_grpcfg group[1];
};
SPDK_STATIC_ASSERT(sizeof(struct idxd_grpcfg) == 48, "size mismatch");
union idxd_wqcfg {
struct {
@ -580,6 +589,10 @@ union idxd_wqcfg {
};
SPDK_STATIC_ASSERT(sizeof(union idxd_wqcfg) == 32, "size mismatch");
struct idxd_wqtbl {
union idxd_wqcfg wq[1];
};
#ifdef __cplusplus
}
#endif

31
lib/idxd/idxd_user.c
View File

@ -184,7 +184,7 @@ idxd_group_config(struct spdk_idxd_device *idxd)
union idxd_enginecap_register enginecap;
union idxd_wqcap_register wqcap;
union idxd_offsets_register table_offsets;
struct idxd_grpcfg *grpcfg;
struct idxd_grptbl *grptbl;
groupcap.raw = spdk_mmio_read_8(&user_idxd->registers->groupcap.raw);
enginecap.raw = spdk_mmio_read_8(&user_idxd->registers->enginecap.raw);
@ -214,33 +214,30 @@ idxd_group_config(struct spdk_idxd_device *idxd)
table_offsets.raw[0] = spdk_mmio_read_8(&user_idxd->registers->offsets.raw[0]);
table_offsets.raw[1] = spdk_mmio_read_8(&user_idxd->registers->offsets.raw[1]);
grpcfg = (struct idxd_grpcfg *)((uint8_t *)user_idxd->registers + (table_offsets.grpcfg *
grptbl = (struct idxd_grptbl *)((uint8_t *)user_idxd->registers + (table_offsets.grpcfg *
IDXD_TABLE_OFFSET_MULT));
/* GRPWQCFG, work queues config */
spdk_mmio_write_8((uint64_t *)&grpcfg->wqs[0], idxd->groups->grpcfg.wqs[0]);
spdk_mmio_write_8((uint64_t *)&grptbl->group[0].wqs[0], idxd->groups->grpcfg.wqs[0]);
/* GRPENGCFG, engine config */
spdk_mmio_write_8((uint64_t *)&grpcfg->engines, idxd->groups->grpcfg.engines);
spdk_mmio_write_8((uint64_t *)&grptbl->group[0].engines, idxd->groups->grpcfg.engines);
/* GRPFLAGS, flags config */
spdk_mmio_write_8((uint64_t *)&grpcfg->flags, idxd->groups->grpcfg.flags.raw);
spdk_mmio_write_8((uint64_t *)&grptbl->group[0].flags, idxd->groups->grpcfg.flags.raw);
/*
* Now write the other groups to zero them out
*/
for (i = 1 ; i < groupcap.num_groups; i++) {
grpcfg = (struct idxd_grpcfg *)((uint8_t *)user_idxd->registers + (table_offsets.grpcfg *
IDXD_TABLE_OFFSET_MULT) + (i * 64));
/* GRPWQCFG, work queues config */
spdk_mmio_write_8((uint64_t *)&grpcfg->wqs[0], 0UL);
spdk_mmio_write_8((uint64_t *)&grptbl->group[i].wqs[0], 0UL);
/* GRPENGCFG, engine config */
spdk_mmio_write_8((uint64_t *)&grpcfg->engines, 0UL);
spdk_mmio_write_8((uint64_t *)&grptbl->group[i].engines, 0UL);
/* GRPFLAGS, flags config */
spdk_mmio_write_8((uint64_t *)&grpcfg->flags, 0UL);
spdk_mmio_write_8((uint64_t *)&grptbl->group[i].flags, 0UL);
}
return 0;
@ -259,12 +256,14 @@ idxd_wq_config(struct spdk_user_idxd_device *user_idxd)
uint32_t wq_size;
union idxd_wqcap_register wqcap;
union idxd_offsets_register table_offsets;
union idxd_wqcfg *wqcfg;
struct idxd_wqtbl *wqtbl;
wqcap.raw = spdk_mmio_read_8(&user_idxd->registers->wqcap.raw);
wq_size = wqcap.total_wq_size;
assert(sizeof(wqtbl->wq[0]) == 1 << (WQCFG_SHIFT + wqcap.wqcfg_size));
SPDK_DEBUGLOG(idxd, "Total ring slots available space 0x%x, so per work queue is 0x%x\n",
wqcap.total_wq_size, wq_size);
@ -283,14 +282,14 @@ idxd_wq_config(struct spdk_user_idxd_device *user_idxd)
table_offsets.raw[1] = spdk_mmio_read_8(&user_idxd->registers->offsets.raw[1]);
queue = idxd->queues;
wqcfg = (union idxd_wqcfg *)((uint8_t *)user_idxd->registers + (table_offsets.wqcfg *
IDXD_TABLE_OFFSET_MULT));
wqtbl = (struct idxd_wqtbl *)((uint8_t *)user_idxd->registers + (table_offsets.wqcfg *
IDXD_TABLE_OFFSET_MULT));
/* Per spec we need to read in existing values first so we don't zero out something we
* didn't touch when we write the cfg register out below.
*/
for (j = 0 ; j < (sizeof(union idxd_wqcfg) / sizeof(uint32_t)); j++) {
queue->wqcfg.raw[j] = spdk_mmio_read_4(&wqcfg->raw[j]);
queue->wqcfg.raw[j] = spdk_mmio_read_4(&wqtbl->wq[0].raw[j]);
}
queue->wqcfg.wq_size = wq_size;
@ -308,7 +307,7 @@ idxd_wq_config(struct spdk_user_idxd_device *user_idxd)
* Now write the work queue config to the device for configured queues
*/
for (j = 0 ; j < (sizeof(union idxd_wqcfg) / sizeof(uint32_t)); j++) {
spdk_mmio_write_4(&wqcfg->raw[j], queue->wqcfg.raw[j]);
spdk_mmio_write_4(&wqtbl->wq[0].raw[j], queue->wqcfg.raw[j]);
}
return 0;