From 3a093d82c3d7d85fb3f1d0af9ecea7b64f9cce28 Mon Sep 17 00:00:00 2001
From: Ziye Yang <ziye.yang@intel.com>
Date: Fri, 2 Apr 2021 20:30:11 +0800
Subject: [PATCH] idxd: Update the definition of register according to the new
 spec.

This patch is used to update the field definition related with
work queue in the header file.

Signed-off-by: Ziye Yang <ziye.yang@intel.com>
Change-Id: I68b81d9dfc2497db89e96f0730785be03dcb8add
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/7225
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: <dongx.yi@intel.com>
Reviewed-by: Changpeng Liu <changpeng.liu@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Community-CI: Mellanox Build Bot
---
 lib/idxd/idxd_spec.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/lib/idxd/idxd_spec.h b/lib/idxd/idxd_spec.h
index 51d52cdcc..5b6980123 100644
--- a/lib/idxd/idxd_spec.h
+++ b/lib/idxd/idxd_spec.h
@@ -331,7 +331,8 @@ union idxd_wqcap_register {
 	struct {
 		uint64_t total_wq_size: 16;
 		uint64_t num_wqs: 8;
-		uint64_t rsvd: 24;
+		uint64_t wqcfg_size: 4;
+		uint64_t rsvd: 20;
 		uint64_t shared_mode: 1;
 		uint64_t dedicated_mode: 1;
 		uint64_t rsvd2: 1;
@@ -470,7 +471,8 @@ union idxd_wqcfg {
 		uint16_t rsvd1;
 		uint32_t mode: 1;
 		uint32_t bof: 1;
-		uint32_t rsvd2: 2;
+		uint32_t wq_ats_disable: 1;
+		uint32_t rsvd2: 1;
 		uint32_t priority: 4;
 		uint32_t pasid: 20;
 		uint32_t pasid_en: 1;