From 39abf01ee22bd46d190fb270ab0e9817bce8412f Mon Sep 17 00:00:00 2001
From: Jim Harris <james.r.harris@intel.com>
Date: Thu, 31 May 2018 06:02:45 -0700
Subject: [PATCH] barrier.h: add spdk_rmb

These are needed in some cases on x86 where a compiler
barrier is not sufficient - for example, ensuring an
rdtsc instruction has executed before subsequent
instructions.

Signed-off-by: Jim Harris <james.r.harris@intel.com>
Change-Id: I339e2dd6138ccb11b1492e70f7c724976ef3038b

Reviewed-on: https://review.gerrithub.io/413145
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
---
 include/spdk/barrier.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/spdk/barrier.h b/include/spdk/barrier.h
index a5f83916e..623d73efd 100644
--- a/include/spdk/barrier.h
+++ b/include/spdk/barrier.h
@@ -60,6 +60,18 @@ extern "C" {
 #error Unknown architecture
 #endif
 
+/** Read memory barrier */
+#ifdef __PPC64__
+#define spdk_rmb()	__asm volatile("lwsync" ::: "memory")
+#elif defined(__aarch64__)
+#define spdk_rmb()	__asm volatile("dsb lt" ::: "memory")
+#elif defined(__i386__) || defined(__x86_64__)
+#define spdk_rmb()	__asm volatile("lfence" ::: "memory")
+#else
+#define spdk_rmb()
+#error Unknown architecture
+#endif
+
 /** Full read/write memory barrier */
 #ifdef __PPC64__
 #define spdk_mb()	__asm volatile("sync" ::: "memory")