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nvme: silence debug logs when waiting for CSTS.RDY transitions

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These can produce a lot of output, which doesn't really give any
additional information.

Signed-off-by: Konrad Sztyber <konrad.sztyber@intel.com>
Change-Id: I572cd203d61c717ce6400f67ef27ec1d7bb54c0c
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/10414
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
Community-CI: Mellanox Build Bot
Reviewed-by: Jacek Kalwas <jacek.kalwas@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com>
This commit is contained in:
Konrad Sztyber 2021-11-25 09:43:41 +01:00 committed by Tomasz Zawadzki
parent 2c32ca4ceb
commit 2f9c97a4f6
1 changed files with 40 additions and 20 deletions
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60
lib/nvme/nvme_ctrlr.c
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@ -1412,15 +1412,17 @@ nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
}; };
static void static void
nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
uint64_t timeout_in_ms) uint64_t timeout_in_ms, bool quiet)
{ {
uint64_t ticks_per_ms, timeout_in_ticks, now_ticks; uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
ctrlr->state = state; ctrlr->state = state;
if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) { if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n", if (!quiet) {
nvme_ctrlr_state_string(ctrlr->state)); NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
nvme_ctrlr_state_string(ctrlr->state));
}
return; return;
} }
@ -1444,15 +1446,33 @@ nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
} }
ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks; ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n", if (!quiet) {
nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms); NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
}
return; return;
inf: inf:
NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n", if (!quiet) {
nvme_ctrlr_state_string(ctrlr->state)); NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
nvme_ctrlr_state_string(ctrlr->state));
}
ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE; ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
} }
static void
nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
uint64_t timeout_in_ms)
{
_nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
}
static void
nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
uint64_t timeout_in_ms)
{
_nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
}
static void static void
nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr) nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
{ {
@ -3652,8 +3672,8 @@ nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct
nvme_ctrlr_get_ready_timeout(ctrlr)); nvme_ctrlr_get_ready_timeout(ctrlr));
} else { } else {
NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n"); NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
NVME_TIMEOUT_KEEP_EXISTING); NVME_TIMEOUT_KEEP_EXISTING);
} }
} }
@ -3691,8 +3711,8 @@ nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct
*/ */
spdk_delay_us(100); spdk_delay_us(100);
} else { } else {
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
NVME_TIMEOUT_KEEP_EXISTING); NVME_TIMEOUT_KEEP_EXISTING);
} }
} }
@ -3730,8 +3750,8 @@ nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE, nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
ctrlr->opts.admin_timeout_ms); ctrlr->opts.admin_timeout_ms);
} else { } else {
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
NVME_TIMEOUT_KEEP_EXISTING); NVME_TIMEOUT_KEEP_EXISTING);
} }
} }
@ -3839,8 +3859,8 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
* If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready. * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
* Wait for the ready bit to be 1 before disabling the controller. * Wait for the ready bit to be 1 before disabling the controller.
*/ */
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
NVME_TIMEOUT_KEEP_EXISTING); NVME_TIMEOUT_KEEP_EXISTING);
rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr); rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
break; break;
@ -3851,8 +3871,8 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
break; break;
case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0: case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS, nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
NVME_TIMEOUT_KEEP_EXISTING); NVME_TIMEOUT_KEEP_EXISTING);
rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr); rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
break; break;
@ -3863,8 +3883,8 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
return rc; return rc;
case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
NVME_TIMEOUT_KEEP_EXISTING); NVME_TIMEOUT_KEEP_EXISTING);
rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1, rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
ctrlr); ctrlr);
break; break;