From 2aa7396d8249a9f774019bcd96c44f53040b4a66 Mon Sep 17 00:00:00 2001
From: Kefu Chai <tchaikov@gmail.com>
Date: Fri, 26 Oct 2018 20:53:21 +0800
Subject: [PATCH] barrier.h: fix load fence on armv8

the weak memory ordering on armv8 can be implemented using

dsb ld

see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/DMB.html

Change-Id: I4db34b87fa659967109adc688cad784018cedaae
Signed-off-by: Kefu Chai <tchaikov@gmail.com>
Reviewed-on: https://review.gerrithub.io/430767
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-on: https://review.gerrithub.io/435672
Reviewed-by: Shuhei Matsumoto <shuhei.matsumoto.xt@hitachi.com>
---
 include/spdk/barrier.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/spdk/barrier.h b/include/spdk/barrier.h
index d4665a2f2..cd670abf2 100644
--- a/include/spdk/barrier.h
+++ b/include/spdk/barrier.h
@@ -64,7 +64,7 @@ extern "C" {
 #ifdef __PPC64__
 #define spdk_rmb()	__asm volatile("sync" ::: "memory")
 #elif defined(__aarch64__)
-#define spdk_rmb()	__asm volatile("dsb lt" ::: "memory")
+#define spdk_rmb()	__asm volatile("dsb ld" ::: "memory")
 #elif defined(__i386__) || defined(__x86_64__)
 #define spdk_rmb()	__asm volatile("lfence" ::: "memory")
 #else