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external_code/nvme: retrieve page size and doorbell stride

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These values are needed for managing a submission/completion queue pair,
which will be added in the subsequent patch.

Signed-off-by: Konrad Sztyber <konrad.sztyber@intel.com>
Change-Id: I80ac0d607160f06a13014b7dea95ae8172290aee
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6670
Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
Community-CI: Mellanox Build Bot
Reviewed-by: Tomasz Zawadzki <tomasz.zawadzki@intel.com>
Reviewed-by: Jim Harris <james.r.harris@intel.com>
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
This commit is contained in:
Konrad Sztyber 2021-02-18 14:06:10 +01:00 committed by Tomasz Zawadzki
parent 7da17fb378
commit 210e0db7e0
1 changed files with 10 additions and 3 deletions
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13
test/external_code/nvme/nvme.c
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@ -42,6 +42,10 @@ struct nvme_ctrlr {
struct spdk_pci_device *pci_device; struct spdk_pci_device *pci_device;
/* Pointer to the MMIO register space */ /* Pointer to the MMIO register space */
volatile struct spdk_nvme_registers *regs; volatile struct spdk_nvme_registers *regs;
/* Stride in uint32_t units between doorbells */
uint32_t doorbell_stride_u32;
/* Controller's memory page size */
uint32_t page_size;
TAILQ_ENTRY(nvme_ctrlr) tailq; TAILQ_ENTRY(nvme_ctrlr) tailq;
}; };
@ -109,9 +113,7 @@ set_pcie_reg_8(struct nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value)
spdk_mmio_write_8(get_pcie_reg_addr(ctrlr, offset), value); spdk_mmio_write_8(get_pcie_reg_addr(ctrlr, offset), value);
} }
void nvme_ctrlr_get_cap(struct nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap); static void
void
nvme_ctrlr_get_cap(struct nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap) nvme_ctrlr_get_cap(struct nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
{ {
get_pcie_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap), &cap->raw); get_pcie_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap), &cap->raw);
@ -171,6 +173,7 @@ pcie_enum_cb(void *ctx, struct spdk_pci_device *pci_dev)
{ {
struct nvme_ctrlr *ctrlr; struct nvme_ctrlr *ctrlr;
TAILQ_HEAD(, nvme_ctrlr) *ctrlrs = ctx; TAILQ_HEAD(, nvme_ctrlr) *ctrlrs = ctx;
union spdk_nvme_cap_register cap;
char addr[32] = {}; char addr[32] = {};
uint64_t phys_addr, size; uint64_t phys_addr, size;
uint16_t cmd_reg; uint16_t cmd_reg;
@ -205,6 +208,10 @@ pcie_enum_cb(void *ctx, struct spdk_pci_device *pci_dev)
cmd_reg |= 0x404; cmd_reg |= 0x404;
spdk_pci_device_cfg_write16(pci_dev, cmd_reg, 4); spdk_pci_device_cfg_write16(pci_dev, cmd_reg, 4);
nvme_ctrlr_get_cap(ctrlr, &cap);
ctrlr->page_size = 1 << (12 + cap.bits.mpsmin);
ctrlr->doorbell_stride_u32 = 1 << cap.bits.dstrd;
TAILQ_INSERT_TAIL(ctrlrs, ctrlr, tailq); TAILQ_INSERT_TAIL(ctrlrs, ctrlr, tailq);
return 0; return 0;