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barrier: ppc64 memory barriers

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Introduce memory barriers for ppc64.

Change-Id: Ie51f959dd8d677f5af3ce6843e5304dd5e24a1e9
Signed-off-by: Jonas Pfefferle <jpf@zurich.ibm.com>
Reviewed-on: https://review.gerrithub.io/383726
Reviewed-by: Ben Walker <benjamin.walker@intel.com>
Reviewed-by: Dariusz Stojaczyk <dariuszx.stojaczyk@intel.com>
Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com>
Tested-by: SPDK Automated Test System <sys_sgsw@intel.com>
This commit is contained in:
PepperJo 2017-10-10 14:19:16 +02:00 committed by Daniel Verkamp
parent 258c5ea47a
commit 1a2dc66189
1 changed files with 9 additions and 0 deletions
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9
include/spdk/barrier.h
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@ -2,6 +2,7 @@
* BSD LICENSE * BSD LICENSE
* *
* Copyright (c) Intel Corporation. * Copyright (c) Intel Corporation.
* Copyright (c) 2017, IBM Corporation.
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -48,10 +49,18 @@ extern "C" {
#define spdk_compiler_barrier() __asm volatile("" ::: "memory") #define spdk_compiler_barrier() __asm volatile("" ::: "memory")
/** Write memory barrier */ /** Write memory barrier */
#ifdef __PPC64__
#define spdk_wmb() __asm volatile("sync" ::: "memory")
#else
#define spdk_wmb() __asm volatile("sfence" ::: "memory") #define spdk_wmb() __asm volatile("sfence" ::: "memory")
#endif
/** Full read/write memory barrier */ /** Full read/write memory barrier */
#ifdef __PPC64__
#define spdk_mb() __asm volatile("sync" ::: "memory")
#else
#define spdk_mb() __asm volatile("mfence" ::: "memory") #define spdk_mb() __asm volatile("mfence" ::: "memory")
#endif
#ifdef __cplusplus #ifdef __cplusplus
} }